User’s Manual

 

 

 

 

 

 

 

IBM PowerPC 750GX and 750GL RISC Microprocessor

 

 

 

 

 

 

 

 

 

 

 

Figure 1-3. System Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Arbitration

 

 

 

 

 

 

 

 

Data Arbitration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Start

 

 

 

 

 

 

 

 

Data Transfer

 

 

 

 

 

 

 

 

Address Transfer

 

 

 

 

750GX

 

 

Data Termination

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transfer Attribute

 

 

 

 

 

 

 

 

Test and Control

 

 

 

 

 

 

 

Address Termination

 

 

 

 

 

 

 

 

Clocks

 

 

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

Processor Status/Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

VDD (I/O)

 

 

 

 

 

 

 

 

 

 

 

The system interface supports address pipelining, which allows the address tenure of one transaction to overlap the data tenure of another. The 750GX can support up to five outstanding transactions on the bus, including up to one snoop copyback, up to four loads, and up to four stores. The extent of the pipelining depends on external arbitration and control circuitry. Similarly, the 750GX supports split-bus transactions for systems with multiple potential bus masters—one device can be master of the address bus while another is master of the data bus. Allowing multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity.

The 750GX’s clocking structure supports a wide range of processor-to-bus clock ratios.

1.2.7 Signals

The 750GX’s signals are grouped as follows:

Address arbitration

The 750GX uses these signals to arbitrate for address-bus mastership.

Address start

This signal indicates that a bus master has begun a transaction on the address

 

bus.

Address transfer

These signals include the address bus and are used to transfer the address.

Transfer attribute

These signals provide information about the type of transfer, such as the transfer

 

size and whether the transaction is burst, write-through, or caching-inhibited.

Address termination

These signals are used to acknowledge the end of the address phase of the trans-

 

action. They also indicate whether a condition exists that requires the address

 

phase to be repeated.

Data arbitration

The 750GX uses these signals to arbitrate for data-bus mastership.

Data transfer

These signals include the data bus and are used to transfer the data.

Data termination

These signals are required after each data beat in a data transfer. In a single-beat

 

transaction, a data termination signal also indicates the end of the tenure. In burst

 

accesses, data termination signals apply to individual beats and indicate the end of

 

the tenure only after the final data beat.

 

 

gx_01.fm.(1.2)

PowerPC 750GX Overview

March 27,2006

Page 37 of 377