IBM 750GL, 750GX rfi, dcbi, mfsr, mtsr, mftb, mtmsr, isync, mtmsr, mfmsr, mfspr, mtmsr, mtspr, tlbie, mfspr, mtspr, mtspr, mfspr, mtspr, mtsrin, mfsrin), tlbsync

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

For example, if the mtmsr sets the MSR[PR] bit, unless an isync immediately follows the mtmsr instruction, a privileged instruction could be executed or privileged access could be performed without causing an exception even though the MSR[PR] bit indicates user mode.

Instruction-Related Exceptions

There are two kinds of exceptions in the 750GX—those caused directly by the execution of an instruction and those caused by an asynchronous event (or interrupts). Either can cause components of the system software to be invoked.

Exceptions can be caused directly by the execution of an instruction as follows:

•An attempt to execute an illegal instruction causes the illegal instruction (program exception) handler to be invoked. An attempt by a user-level program to execute the supervisor-level instructions listed below causes the privileged instruction (program exception) handler to be invoked:

–Data Cache Block Invalidate (dcbi)

–Move-from Machine State Register (mfmsr)

–Move-from Special Purpose Register (mfspr)

–Move-from Segment Register (mfsr)

–Move-from Segment Register Indirect (mfsrin)

–Move-to Machine State Register (mtmsr)

–Move-to Special Purpose Register (mtspr)

–Move-to Segment Register (mtsr)

–Move-to Segment Register Indirect (mtsrin)

–Return from Exception (rfi)

–TLB Invalidate Entry (tlbie)

–TLB Synchronize (tlbsync)

Note that the privilege level of the mfspr and mtspr instructions depends on the SPR encoding.

•Any mtspr, mfspr, or Move-from Time Base (mftb) instruction with an invalid SPR (or Time Base Regis- ter [TBR]) field causes an illegal type program exception. Likewise, a program exception is taken if user- level software tries to access a supervisor-level SPR. An mtspr instruction executing in supervisor mode (MSR[PR] = 0) with the SPR field specifying HID1 or PVR (read-only registers) executes as a no-op.

•An attempt to access memory that is not available (page fault) causes the ISI or DSI exception handler to be invoked.

•The execution of an sc instruction invokes the system-call exception handler that permits a program to request the system to perform a service.

•The execution of a trap instruction invokes the program exception trap handler.

•The execution of an instruction that causes a floating-point exception while exceptions are enabled in the MSR invokes the program exception handler.

A detailed description of exception conditions is provided in Chapter 4, Exceptions, on page 151.

2.3.3 Instruction Set Overview

This section provides a brief overview of the PowerPC instructions implemented in the 750GX and highlights any special information about how the 750GX implements a particular instruction. Note that the categories used in this section correspond to those used in Chapter 4, “Addressing Modes and Instruction Set

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