User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

•64-bit floating-point unit (FPU)

•Load/store unit (LSU)

•System register unit (SRU)

Figure 6-1represents a generic pipelined execution unit.

Figure 6-1. Pipelined Execution Unit

 

 

 

Stage 1

 

 

Stage 2

 

 

Stage 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock 0

 

 

Instruction A

 

 

—

 

 

—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock 1

 

 

Instruction B

 

 

Instruction A

 

 

—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock 2

 

 

Instruction C

 

 

Instruction B

 

 

Instruction A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock 3

 

 

Instruction D

 

 

Instruction C

 

 

Instruction B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The 750GX can retire two instructions in every clock cycle. In general, the 750GX processes instructions in four stages—fetch, decode/dispatch, execute, and complete as shown in Figure 6-2. Note that the example of a pipelined execution unit in Figure 6-1is similar to the 3-stage FPU pipeline in Figure 6-2.

Figure 6-2. Superscalar/Pipeline Diagram

Fetch

BPU

Decode/Dispatch

Maximum 4-instruction fetch per clock cycle

Maximum 3-instruction dispatch per clock cycle (includes one branch instruction)

Execute Stage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPU1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPU2

 

 

 

 

 

 

 

LSU1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRU

 

FPU3

 

IU1

 

IU2

 

LSU2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Complete (Write-back)

Maximum 2-instruction completion per

clock cycle

 

 

Instruction Timing

gx_06.fm.(1.2)

Page 212 of 377

March 27, 2006