IBM 750GL, 750GX 6.4 Execution-UnitTimings, mtspr, 6.3.2.7 Instruction Serialization, 6.4.1 Branch Processing Unit Execution Timing

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

When the dispatch unit dispatches an instruction to its execution unit, it allocates a Rename Register (or registers) for the results of that instruction. If an instruction is dispatched to a reservation station associated with an execution unit due to a data dependency, the dispatcher also provides a tag to the execution unit identifying the Rename Register that forwards the required data at completion. When the source data reaches the rename register, execution can begin.

Instruction results are transferred from the Rename Registers to the architected registers by the completion unit when an instruction is retired from the completion queue, provided no exceptions precede it and any predicted branch conditions have been resolved correctly. If a branch prediction was incorrect, the instructions fetched along the predicted path are flushed from the completion queue, and any results of those instructions are flushed from the Rename Registers.

6.3.2.7 Instruction Serialization

Although the 750GX can dispatch and complete two instructions per cycle, so-called serializing instructions limit dispatch and completion to one instruction per cycle. There are three types of instruction serialization:

Execution	Execution-serialized instructions are dispatched, held in the functional unit, and do
	not execute until all prior instructions have completed. A functional unit holding an
	execution-serialized instruction will not accept further instructions from the
	dispatcher. For example, execution serialization is used for instructions that
	modify nonrenamed resources. Results from these instructions are generally not
	available or forwarded to subsequent instructions until the instruction completes
	(using a Move-to Special Purpose Register [mtspr] instruction to write to an LR or
	CTR does provide forwarding to branch instructions).

Completion (also referred to as post-dispatch or tail serialization)

Refetch (flush)

Completion-serialized instructions inhibit dispatching of subsequent instructions until the serialized instruction completes. Completion serialization is used for instructions that bypass the normal rename mechanism.

Refetch-serialized instructions inhibit dispatch of subsequent instructions and force refetching of subsequent instructions after completion.

6.4 Execution-Unit Timings

The following sections describe instruction timing considerations within each of the respective execution units in the 750GX.

6.4.1 Branch Processing Unit Execution Timing

Flow-control operations (conditional branches, unconditional branches, and traps) are typically expensive to execute in most machines because they disrupt normal flow in the instruction stream. When a change in program flow occurs, the IQ must be reloaded with the target instruction stream. Previously issued instructions will continue to execute while the new instruction stream makes its way into the IQ. However, depending on whether the target instruction is in the BTIC, instruction L1 cache, L2 cache, or in system memory, some opportunities might be missed to execute instructions. The example in Section 6.3.2.3, Cache Miss, on page 222 illustrates this situation.

gx_06.fm.(1.2)	Instruction Timing
March 27, 2006	Page 225 of 377