IBM 750GL, 750GX mtspr, mfspr, 2.1.5 L2 Cache Control Register (L2CR)

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.1.5 L2 Cache Control Register (L2CR)

The L2 Cache Control Register is a supervisor-level, implementation-specific SPR used to configure and operate the L2 cache. It is cleared by a hard reset or power-on reset.

The L2 cache interface is described in Chapter 9, L2 Cache, on page 323. The L2CR register can be accessed with the mtspr and mfspr instructions using SPR 1017.

L2E	CE
0	1

Reserved

2 3 4 5 6 7 8

DO

9

GI	Reserved	WT	TS			Reserved				LOCKLO	LOCKHI	SHEE	SHERR		LOCK			IO		Reserved		IP
10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29		30	31

Bits	Field Name	Description
0	L2E	L2 enable. Enables and disables the operation of the L2 cache, starting with the next
		transaction.
1	CE	L2 double-bit error checkstop enable. L2 cache double-bit errors can result in a checkstop
		condition.
2:8	Reserved	Reserved.
		L2 data-only. Setting this bit inhibits the caching of instructions in the L2 cache. All
9	DO	accesses from the L1 instruction cache are treated as cache-inhibited by the L2 cache
		(bypass L2 cache, no L2 tag look-up performed).
10	GI	L2 global invalidate. Setting GI invalidates the L2 cache globally by clearing the L2 status
		bits.
11	Reserved	Reserved.
12	WT	L2 write-through. Setting WT selects write-through mode (rather than the default copy-
		back mode) so all writes to the L2 cache also write through to the 60x bus.
		L2 test support. Setting TS causes cache-block pushes from the L1 data cache that result
13	TS	from dcbf and dcbst instructions to be written only into the L2 cache and marked valid,
		rather than being written only to the 60x bus and marked invalid in the L2 cache in case of
		a hit. If TS is set, it causes single-beat store operations that miss in the L2 cache to be
		discarded.
14:19	Reserved	Reserved.
20	LOCKLO	Lock lower half of the L2 cache (ways 0 and 1). This provides a form of backward compat-
		ibility for L2 locking. New applications should use bits 24:25.
21	LOCKHI	Lock upper half of the L2 cache (ways 2 and 3). This provides a form of backward com-
		patibility for L2 locking. New applications should use bits 26:27.
22	SHEE	Snoop hit in locked line error enable. Enables a snoop hit in a locked line to raise a
		machine check.
23	SHERR	Snoop hit in locked line error. Set by a snoop hit to a locked line. Once set, this sticky bit
		remains set until cleared by a mtspr to the L2CR.
24:27	LOCK	Cache lock control. Setting one or more of bits 24, 25, 26, and 27 locks ways 0, 1, 2, and
		3 respectively
		L2 instruction-only. Setting this bit inhibits the caching of data in the L2 cache. All
28	IO	accesses from the L1 data cache are treated as cache-inhibited by the L2 cache (bypass
		L2 cache, no L2 tag look-up performed).
29:30	Reserved	Reserved.
31	IP	L2 global invalidate in progress (read only). This read-only bit indicates whether an L2
		global invalidate is occurring.
gx_02.fm.(1.2)		Programming Model
March 27, 2006		Page 81 of 377