IBM 750GL, 750GX manual 144

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 3-5. Response to Snooped Bus Transactions (Page 2 of 3)

Snooped Transaction	TT[0–4]	750GX Response
		A write-with-kill operation is a burst transaction initiated due to a castout, caching-
		enabled push, or snoop copy-back.
Write-with-kill	00110	• If the address hits in the cache, the cache block is placed in the invalid (I) state
		(killing modified data that might have been in the block).
		• If the address misses in the cache, no action is taken.
		Any reservation associated with the address is canceled.
		A read operation is used by most single-beat and burst load transactions on the bus.
		For single-beat, caching-inhibited read transaction:
		• If the addressed cache block is in the exclusive (E) state, the cache block
		remains in the exclusive (E) state.
		• If the addressed cache block is in the modified (M) state, the 750GX asserts
		ARTRY and initiates a push of the modified block out of the cache, and the
		cache block is placed in the exclusive (E) state.
Read	01010	• If the address misses in the cache, no action is taken.
		For burst read transactions:
		• If the addressed cache block is in the exclusive (E) state, the cache block is
		placed in the invalid (I) state.
		• If the addressed cache block is in the modified (M) state, the 750GX asserts
		ARTRY and initiates a push of the modified block out of the cache, and the
		cache block is placed in the invalid (I) state.
		• If the address misses in the cache, no action is taken.
		A RWITM operation is issued to acquire exclusive use of a memory location for the
		purpose of modifying it.
		• If the addressed cache block is in the exclusive (E) state, the cache block is
Read-with-intent-to-modify	01110	placed in the invalid (I) state.
(RWITM)		• If the addressed cache block is in the modified (M) state, the 750GX asserts
		ARTRY and initiates a push of the modified block out of the cache, and the
		cache block is placed in the invalid (I) state.
		• If the address misses in the cache, no action is taken.
		Write-with-flush-atomic operations occur after the processor issues an stwcx.
		instruction.
		• If the addressed cache block is in the exclusive (E) state, the cache block is
		placed in the invalid (I) state.
Write-with-flush-atomic	10010	• If the addressed cache block is in the modified (M) state, the 750GX asserts
		ARTRY and initiates a push of the modified block out of the cache, and the
		cache block is placed in the invalid (I) state.
		• If the address misses in the cache, no action is taken.
		Any reservation is canceled, regardless of the address.
Reserved	10110	—
Read-atomic	11010	Read atomic operations appear on the bus in response to lwarx instructions and
		generate the same snooping responses as read operations.
Read-with-intent-to-modify-	11110	The RWITM atomic operations appear on the bus in response to stwcx. instructions
atomic		and generate the same snooping responses as RWITM operations.
Reserved	00011	—
Reserved	00111	—

Instruction-Cache and Data-Cache Operation	gx_03.fm.(1.2)
Page 144 of 377	March 27, 2006