User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Fetch

The process of bringing instructions from the system memory (such as a cache or

 

the main memory) into the instruction queue.

Folding (branch folding)

On the 750GX, a branch is expunged from (folded out of) the instruction queue via

 

the dispatch mechanism, without being either passed to an execution unit or given

 

a position in the completion queue. Subsequent instructions are fetched from

 

sequential addresses for branches-not-taken and from target addresses for

 

branches-taken.

Finish

Finishing occurs in the last cycle of execution. (This could also be the first cycle of

 

execution for instructions that only require one cycle for execution.) In this cycle,

 

the output Rename Register and the completion queue entry are updated to indi-

 

cate that the instruction has finished executing.

Latency

The number of clock cycles necessary to execute an instruction and make ready

 

the results of that execution for a subsequent instruction.

Pipeline

In the context of instruction timing, the term ‘pipeline’ refers to the interconnection

 

of the stages. The events necessary to process an instruction are broken into

 

several cycle-length tasks to allow work to be performed on several instructions

 

simultaneously—analogous to an assembly line. As an instruction is processed, it

 

passes from one stage to the next. When it completes one stage, that stage

 

becomes available for the next instruction.

 

Although an individual instruction can take many cycles to complete (the number of

 

cycles is called instruction latency), pipelining makes it possible to overlap the

 

processing so that the throughput (number of instructions completed per cycle) is

 

greater than if pipelining were not implemented.

Program order

The order of instructions in an executing program. More specifically, this term is

 

used to refer to the original order in which program instructions are fetched into the

 

instruction queue from the system memory.

Rename register

Temporary buffers used to hold either source or destination values for instructions

 

that are in a stage of execution. This simplifies the passing of data outside of the

 

General Purpose Register (GPR) file between instructions during execution.

Reservation station

A buffer between the dispatch and execution units where instructions await execu-

 

tion.

Retirement

Removal of a completed instruction from the completion queue. At this time, any

 

output from the completed instruction is written to the appropriate architected desti-

 

nation register. This might be a GPR, a Floating Point Register (FPR), or a Condi-

 

tion Register (CR) field.

Instruction Timing

gx_06.fm.(1.2)

Page 210 of 377

March 27, 2006