IBM 750GL, 750GX manual Notes:

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 5-3. Translation Exception Conditions (Page 2 of 2)

Condition	Description	Exception
Instruction fetch from direct-store seg-	Attempt to fetch instruction when SR[T] = 1	ISI exception
ment		SRR1[3] =1
Data access to direct-store segment	Attempt to perform load or store (including floating-point	DSI exception
(including floating-point accesses)	(FP) load or store) when SR[T] = 1	DSISR[5] =1
Instruction fetch from guarded memory	Attempt to fetch instruction when MSR[IR] = 1 and either	ISI exception
	matching xBAT[G] = 1, or no matching BAT entry and	SRR1[3] =1
	PTE[G] = 1

The state saved by the processor for each of these exceptions contains information that identifies the address of the failing instruction. See Chapter 4, Exceptions, on page 151 for a more detailed description of exception processing.

In addition to the translation exceptions, there are other MMU-related conditions (some of them defined as implementation-specific, and therefore not required by the architecture) that can cause an exception to occur.

These exception conditions map to processor exceptions as shown in Table 5-4. The only MMU exception conditions that occur when MSR[DR] = 0 are those that cause an alignment exception for data accesses. For more detailed information about the conditions that cause an alignment exception (in particular for string/multiple instructions), see Section 4.5.6, Alignment Exception (0x00600), on page 170.

Notes:

•Some exception conditions depend upon whether the memory area is set up as write-though (W = 1) or caching-inhibited (I = 1).

•These bits are described fully in “Memory/Cache Access Attributes,” in Chapter 5, “Cache Model and Memory Coherency,” of the PowerPC Microprocessor Family: The Programming Environments Manual.

•Also see Chapter 4, Exceptions, on page 151 and Chapter 6, “Exceptions,” in the PowerPC Microproces- sor Family: The Programming Environments Manual for a complete description of the SRR1 and DSISR bit settings for these exceptions.

Table 5-4. Other MMU Exception Conditions for the 750GX Processor (Page 1 of 2)

Condition	Description	Exception
Data Cache Block Set to Zero (dcbz) with	dcbz instruction to write-through or cache-	Alignment exception (not required by archi-
W = 1 or I = 1	inhibited segment or block	tecture for this condition)
Load Word and Reserve Indexed (lwarx),
Store Word Conditional Indexed (stwcx).,	Reservation instruction or external control	DSI exception
External Control In Word Indexed (eciwx),
	instruction when SR[T] = 1	DSISR[5] = 1
or External Control Out Word Indexed
(ecowx) instruction to direct-store segment
Floating-point load or store to direct-store	Floating-point memory access when SR[T]	See data access to direct-store segment in
segment	=1	Table 5-3on page 192.
	A DSI exception is taken when a load or	DSI exception
Load or store that results in a direct-store		For additional information, see
	store is attempted to a direct-store segment
error	(SR[T] = 1)	Section 4.5.3, DSI Exception (0x00300), on
		page 169.

gx_05.fm.(1.2)	Memory Management
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