User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 6-9. Load-and-Store Instructions

(Page 3 of 4)

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Mnemonic

 

Primary

Extended

Unit

Cycles

Serialization

 

Opcode

Opcode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfd

 

54

—

LSU

2:1

—

Double

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfdu

 

55

—

LSU

2:1

—

Double with Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfdux

 

 

 

 

 

 

Double with Update

 

31

759

LSU

2:1

—

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfdx

 

31

727

LSU

2:1

—

Double Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point as

stfiwx

 

31

983

LSU

2:1

—

Integer Word Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfs

 

52

—

LSU

2:1

—

Single

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfsu

 

53

—

LSU

2:1

—

Single with Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfsux

 

 

 

 

 

 

Single with Update

 

31

695

LSU

2:1

—

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Floating-Point

stfsx

 

31

663

LSU

2:1

—

Single Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Halfword

sth

 

44

—

LSU

2:1

—

 

 

 

 

 

 

 

 

Store Halfword Byte-

sthbrx

 

31

918

LSU

2:1

—

Reverse Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Halfword with

sthu

 

45

—

LSU

2:1

—

Update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Halfword with

sthux

 

31

439

LSU

2:1

—

Update Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Halfword Indexed

sthx

 

31

407

LSU

2:1

—

 

 

 

 

 

 

 

 

Store Multiple Word

stmw

 

47

—

LSU

2 + n 3

Execution

Store String Word

stswi

 

31

725

LSU

2 + n 3

Execution

Immediate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store String Word

stswx

 

31

661

LSU

2 + n 3

Execution

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Word

stw

 

36

—

LSU

2:1

—

 

 

 

 

 

 

 

 

Store Word Byte-

stwbrx

 

31

662

LSU

2:1

—

Reverse Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Word Conditional

stwcx.

 

31

150

LSU

8:8

Execution

Indexed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Store Word with Update

stwu

 

37

—

LSU

2:1

—

 

 

 

 

 

 

 

 

1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for

back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete

the instruction to the cache, which stays busy keeping subsequent cache operations from executing.

 

2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space,

throughput is at least 11 cycles.

 

 

 

 

 

 

3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n

is the number of words accessed by the instruction.

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Timing

gx_06.fm.(1.2)

Page 246 of 377

March 27, 2006