IBM 750GL, 750GX State, Timing, 7.2.16 Power and Ground Signals, 7.2.15.4 PLL Range (PLL_RNG[0:1])—Input

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

7.2.15.4 PLL Range (PLL_RNG[0:1])—Input

State	Asserted/	Configures the PLL operating-frequency range. Internal core clock
	Negated	frequency must be within the specified range.
Timing	Asserted/	Must remain stable during normal operation; should only be changed during
	Negated	the assertion of HRESET. These bits are readable through bits PRE[5:6] in
		the HID1.

7.2.16 Power and Ground Signals

The 750GX provides the following connections for power and ground:

•VDD—The VDD signals provide the supply voltage connection for the processor core.

•OVDD—The OVDD signals provide the supply voltage connection for the system interface drivers.

•AVDD—The AVDD power signal provides power to the clock generation phase-locked loop. See the PowerPC 750GX Datasheet for information on how to use this signal.

•GND and OGND—The GND and OGND signals provide the connection for grounding the 750GX. On the 750GX, there is no electrical distinction between the GND and OGND signals.

Signal Descriptions	gx_07.fm.(1.2)
Page 278 of 377	March 27, 2006