IBM 750GL, 750GX Acronyms and Abbreviations, Index, Revision Log

		User’s Manual
	IBM PowerPC 750GX and 750GL RISC Microprocessor
11.1	Performance-Monitor Interrupt ............................................................................................	........ 349
11.2	Special-Purpose Registers Used by Performance Monitor .........................................................	350
11.2.1 Performance-Monitor Registers .........................................................................................		351
	11.2.1.1 Monitor Mode Control Register 0 (MMCR0) ...............................................................	351
	11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0) ....................................................	351
	11.2.1.3 Monitor Mode Control Register 1 (MMCR1) ...............................................................	351
	11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1) ....................................................	351
	11.2.1.5 Performance-Monitor Counter Registers (PMCn) ......................................................	351
	11.2.1.6 User Performance-Monitor Counter Registers (UPMC1–UPMC4) ............................	354
	11.2.1.7 Sampled Instruction Address Register (SIA) ..............................................................	355
	11.2.1.8 User Sampled Instruction Address Register (USIA) ...................................................	355
11.3	Event Counting ............................................................................................................................	355
11.4	Event Selection ...........................................................................................................................	356
11.5	Notes ...........................................................................................................................................	356
11.6	Debug Support ............................................................................................................................	357
11.6.1 Overview ............................................................................................................................		357
11.6.2 Data-Address Breakpoint ................................................................................................		.. 357
11.7	JTAG/COP Functions .......................................................................................................	........... 357
11.7.1 Introduction ........................................................................................................................		357
11.7.2 Processor Resources Available through JTAG/COP Serial Interface ...............................		357
11.8	Resets .........................................................................................................................................	359
11.8.1 Hard Reset .............................................................................................................		........... 359
11.8.2 Soft Reset ..........................................................................................................................		359
11.8.3 Reset Sequence .........................................................................................................		....... 360
11.9	Checkstops .................................................................................................................................	361
11.9.1 Checkstop Sources ......................................................................................................		..... 361
11.9.2 Checkstop Control Bits .................................................................................................		..... 361
11.9.3 Open-Collector-Driver States during Checkstop ...............................................................		362
11.9.4 Vacancy Slot Application ...............................................................................................		.... 362
11.10 750GX Parity .............................................................................................................................		363
11.10.1 Parity Control and Status .............................................................................................		.... 364
11.10.2 Enabling Parity Error Detection .......................................................................................		364
11.10.3 Parity Errors .........................................................................................................		............ 364
Acronyms and Abbreviations ...................................................................................		365
Index	........................................................................................................................	.... 369
Revision Log ..............................................................................................................		377

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