IBM 750GL, 750GX manual 66

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Bits	Field Name				Description
		Nap mode enable. Operates in conjunction with MSR[POW].
9	NAP2	0	Nap mode disabled.
		1	Nap mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is
			set. In nap mode, the PLL and the time base remain active.
		Sleep mode enable. Operates in conjunction with MSR[POW].
		0	Sleep mode disabled.
		1	Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit
10	SLEEP2		is set. QREQ is asserted to indicate that the processor is ready to enter sleep
			mode. If the system logic determines that the processor can enter sleep mode,
			the quiesce acknowledge signal, QACK, is asserted back to the processor. Once
			QACK assertion is detected, the processor enters sleep mode after several pro-
			cessor clocks. At this point, the system logic can turn off the PLL by first configur-
			ing PLL_CFG[0:4] to PLL bypass mode, then disabling SYSCLK.
		Dynamic power management enable.
		0	Dynamic power management is disabled.
11	DPM	1	Functional units enter a low-power mode automatically if the unit is idle. This
			does not affect operational performance and is transparent to software or any
			external hardware.
12	RISEG	Read Instruction Segment Register (for test only).
13	—	Reserved.
		Miss-under-Miss enable.
14	MUM	0	Function disabled.
		1	Function enabled.
		Not a hard reset (software-use only). Helps software distinguish a hard reset from a soft
		reset.
15	NHR	0	A hard reset has occurred if software previously set this bit.
		1	A hard reset has not occurred. If software sets this bit after a hard reset, when a
			reset occurs and this bit remains set, software can tell it was a soft reset.
		Instruction-cache enable
		0	The instruction cache is neither accessed nor updated. All pages are accessed
			as if they were marked cache-inhibited (WIM = X1X). Potential cache accesses
			from the bus (snoop and cache operations) are ignored. In the disabled state for
16	ICE		the L1 caches, the cache tag state bits are ignored and all accesses are propa-
			gated to the L2 cache or bus as single-beat transactions. For those transactions,
			however, Cache Inhibit (CI) reflects the original state determined by address
			translation regardless of cache disabled status. ICE is zero at power-up.
		1	The instruction cache is enabled
		Data-cache enable
		0	The data cache is neither accessed nor updated. All pages are accessed as if
			they were marked cache-inhibited (WIM = X1X). Potential cache accesses from
			the bus (snoop and cache operations) are ignored. In the disabled state for the
17	DCE		L1 caches, the cache tag state bits are ignored and all accesses are propagated
			to the L2 cache or bus as single-beat transactions. For those transactions, how-
			ever,	CI	reflects the original state determined by address translation regardless
			of cache disabled status. DCE is zero at power-up.
		1	The data cache is enabled.

1. For additional information, see Section 11.9, Checkstops, on page 361.

2. For additional information about power-saving modes, see Table 10-2, HID0 Power Saving Mode Bit Settings, on page 337.

Programming Model	gx_02.fm.(1.2)
Page 66 of 377	March 27, 2006