
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
7.2.9.3State | Asserted | The 750GX initiates a |
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| HID0[EMCP] are set. If MSR[ME] is cleared and HID0[EMCP] is set, the |
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| 750GX must terminate operation by internally gating off all clocks, and |
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| releasing all outputs (except CKSTP_OUT) to the |
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| HID0[EMCP] is cleared, the 750GX ignores the interrupt condition. The MCP |
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| signal must be held asserted for two bus clock cycles. |
| Negated | Indicates that normal operation should proceed. |
Timing | Assertion | May occur at any time and may be asserted asynchronously to the input |
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| clocks. The MCP input is negative |
| Negation | May be negated two bus cycles after assertion. |
State | Asserted | Indicates that the 750GX must enter the checkstop state and terminate oper- | ||
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| ation. The 750GX will internally gate off all clocks and remain in this state | ||
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| while CKSTP_IN is asserted. The 750GX will also release all outputs (except | ||
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| CKSTP_OUT) to the | ||
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| Once CKSTP_IN has been asserted it must remain asserted until the system | ||
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| has been reset. | ||
| Negated | Indicates that normal operation should proceed. | ||
Timing | Assertion | May occur at any time and may be asserted asynchronously to the input | ||
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| clocks. | ||
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| Negation | May occur any time after the | CKSTP_IN | output has been asserted. |
Note that the CKSTP_OUT signal is an
State | Asserted | Indicates that a checkstop condition has been detected, and the processor | ||
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| has ceased operation. | ||
| Negated | Indicates that the processor is operating normally. | ||
Timing | Assertion | Might occur at any time and can be asserted asynchronously to input clocks. | ||
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| High | Requires | HRESET. |
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| Impedance |
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Note: CKSTP_OUT operates as an
gx_07.fm.(1.2) | Signal Descriptions |
March 27, 2006 | Page 271 of 377 |