User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
are not broadcast, unless broadcast is enabled through the HID0[ABE] configuration bit. Note that dcbi, dcbf, dcbst, and dcbz do broadcast to the 750GX’s L2 cache, regardless of HID0[ABE]. The icbi instruction is never broadcast.
3.4.2.1 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)
The dcbt and dcbtst instructions provide potential system performance improvement through the use of software -initiated prefetch hints. The 750GX treats these instructions identically (that is, a dcbtst instruction behaves exactly the same as a dcbt instruction on the 750GX). Note that PowerPC implementations are not required to take any action based on the execution of these instructions, but they might choose to prefetch the cache block corresponding to the effective address into their cache.
The 750GX loads the data into the cache when the address hits in the translation lookaside buffer (TLB) or the BAT, is permitted load access from the addressed page, is not directed to a direct-store segment, and is directed at a cacheable page. Otherwise, the 750GX treats these instructions as no-ops. The data brought into the cache as a result of this instruction is validated in the same manner that a load instruction would be (that is, it is marked as exclusive). The memory reference of a dcbt (or dcbtst) instruction causes the reference bit to be set. Note also that the successful execution of the dcbt (or dcbtst) instruction affects the state of the TLB and cache LRU bits as defined by the PLRU algorithm.
3.4.2.2 Data Cache Block Zero (dcbz)The effective address is computed, translated, and checked for protection violations as defined in the PowerPC Architecture. The dcbz instruction is treated as a store to the addressed byte with respect to address translation and protection.
If the block containing the byte addressed by the EA is in the data cache, all bytes are cleared, and the tag is marked as modified (M). If the block containing the byte addressed by the EA is not in the data cache and the corresponding page is caching-enabled, the block is established in the data cache without fetching the block from main memory, and all bytes of the block are cleared, and the tag is marked as modified (M).
If the contents of the cache block are from a page marked memory coherence required (M=1), an address- only bus transaction is run prior to clearing the cache block. The dcbz instruction is the only cache-control instruction that causes a broadcast on the 60x bus (when M = 1) to maintain coherency. The other cache- control instructions are not broadcast unless broadcasting is specifically enabled through the HID0[ABE] configuration bit. The dcbz instruction executes regardless of whether the cache is locked, but if the cache is disabled, an alignment exception is generated. If the page containing the byte addressed by the EA is caching-inhibited or write-through, then the system alignment exception handler is invoked. BAT and TLB protection violations generate DSI exceptions.
Note: If the target address of a dcbz instruction hits in the L1 cache, the 750GX requires four internal clock cycles to rewrite the cache block to zeros. On the first clock, the block is remarked as valid-unmodified, and on the last clock the block is marked as valid-modified. If a snoop request to that address is received during the middle two clocks of the dcbz operation, the 750GX does not properly react to the snoop operation or generate an address retry (by an ARTRY assertion) to the other master. The other bus master continues reading the data from system memory, and both the 750GX and the other bus master end up with different copies of the data. In addition, if the other bus master has a cache, the cache block is marked valid in both caches, which is not allowed in the 750GX’s 3-state cache environment.
Instruction-Cache and Data-Cache Operation | gx_03.fm.(1.2) |
Page 134 of 377 | March 27, 2006 |
