User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

•The execution units process instructions from their reservation stations using the operands provided from dispatch, and notifies the completion stage when the instruction has finished execution. With the excep- tion of multiply and divide, integer instructions complete execution in a single cycle.

The FPU has three stages (multiply, add, and normalize) for processing floating-point arithmetic. All sin- gle-precision arithmetic (add, subtract, multiply, and multiply/add) instructions are processed without stalls at each stage. They have a 1-cycle throughput and a 3-cycle latency. Three different arithmetic instructions can be in the execution unit at one time, with one instruction completing execution each cycle. Double-precision arithmetic multiply requires two cycles in the multiply stage, one cycle in the add stage, and one cycle in the normalize stage, which yields a 2-cycle throughput and a 4-cycle latency. All divide instructions require multiple cycles in the first stage for processing.

The load/store unit has two reservation registers and two pipeline stages. The first stage is for effective address calculation and the second stage is for MMU translation and accessing the L1 data cache. Load instructions have a 1-cycle throughput and a 2-cycle latency.

In the case of an internal exception, the execution unit reports the exception to the completion pipeline stage and (except for the FPU) discontinues instruction execution until the exception is handled. The exception is not signaled until it is determined that all previous instructions have completed to a point where they will not signal an exception.

•The completion unit retires instructions from the bottom two positions of the completion queue in program order. This maintains the correct architectural machine state and transfers execution results from the rename buffers to the GPRs and FPRs (and CTR and LR, for some instructions) as instructions are retired. If the completion logic detects an instruction causing an exception, all subsequent instructions are cancelled, their execution results in rename buffers are discarded, and instructions are fetched from the appropriate exception vector.

Because the PowerPC Architecture can be applied to such a wide variety of implementations, instruction timing varies among PowerPC processors. For a detailed discussion of instruction timing with examples and a table of latencies for each execution unit, see Chapter 6, Instruction Timing, on page 209.

1.10 Power Management

The 750GX provides the following four power modes, selectable by setting the appropriate control bits in the MSR and HID0 registers:

Full-power

This is the default power state of the 750GX. The 750GX is fully powered, and the

 

internal functional units are operating at the full processor clock speed. If the

 

dynamic power management mode is enabled, functional units that are idle will

 

automatically enter a low-power state without affecting performance, software

 

execution, or external hardware.

Doze

All the functional units of the 750GX are disabled except for the Time Base/Decre-

 

menter Registers and the bus snooping logic. When the processor is in doze mode,

 

an external asynchronous interrupt, a system management interrupt, a decre-

 

menter exception, a hard or soft reset, or a machine check brings the 750GX into

 

the full-power state. The 750GX in doze mode maintains the PLL in a fully powered

 

state and locked to the system external clock input (SYSCLK) so a transition to the

 

full-power state takes only a few processor clock cycles.

PowerPC 750GX Overview

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March 27,2006