User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
The 750GX selects 64-bit or 32-bit data bus mode at startup by sampling the state of the TLBISYNC signal at the negation of HRESET. If the TLBISYNC signal is negated at the negation of HRESET, the 750GX enters 64-bit data mode. If TLBISYNC is asserted at the negation of HRESET, the 750GX enters 32-bit data mode.
Table 8-3on page 296 describes the burst ordering when the 750GX is in 32-bit mode.
The aligned data-transfer cases for 32-bit data bus mode are shown in Table 8-6. All of the transfers require a single data beat (if caching-inhibited or write-through) except for double-word cases which require two data beats. The double-word case is only generated by the 750GX for load or store double operations to/from the Floating Point Registers. All caching-inhibited instruction fetches are performed as word operations.
Misaligned data transfers in the 32-bit bus mode is the same as in the 64-bit bus mode with the exception that only DH[0-31] data lines are used. Table 8-7shows examples of 4-byte misaligned transfers starting at each possible byte address within a double word.
8.6.2 No-DRTRY ModeThe 750GX supports an optional mode to disable the use of the data retry function provided through the DRTRY signal. The no-DRTRY mode allows the forwarding of data during load operations to the internal CPU one bus cycle sooner than in the normal bus protocol.
The 60x bus protocol specifies that, during load operations, the memory system can, normally, cancel data that was read by the master on the bus cycle after TA was asserted. In the 750GX implementation, this late cancellation protocol requires the 750GX to hold any loaded data at the bus interface for one additional bus clock to verify that the data is valid before forwarding it to the internal CPU. For systems that do not implement the DRTRY function, the 750GX provides an optional no-DRTRY mode that eliminates this 1-cycle stall during all load operations, and allows for the forwarding of data to the internal CPU immediately when TA is recognized.
When the 750GX is in the no-DRTRY mode, data can no longer be cancelled the cycle after it is acknowledged by an assertion of TA. Data is immediately forwarded to the CPU internally, and any attempt at late cancellation by the system might cause improper operation by the 750GX.
When the 750GX is following normal bus protocol, data might be cancelled the bus cycle after TA by either of two means—late cancellation by DRTRY, or late cancellation by ARTRY. When no-DRTRY mode is selected, both cancellation cases must be disallowed in the system design for the bus protocol.
When no-DRTRY mode is selected for the 750GX, the system must ensure that DRTRY is not asserted to the 750GX. If it is asserted, it can cause improper operation of the bus interface. The system must also ensure that an assertion of ARTRY by a snooping device occurs before or coincident with the first assertion of TA to the 750GX, but not on the cycle after the first assertion of TA.
Other than the inability to cancel data that was read by the master on the bus cycle after TA was asserted, the bus protocol for the 750GX is identical to that for the basic transfer bus protocols described in this section, including 32-bit data-bus mode.
The 750GX selects the desired DRTRY mode at startup by sampling the state of the DRTRY signal itself at the negation of the HRESET signal. If the DRTRY signal is negated at the negation of HRESET, normal operation is selected. If the DRTRY signal is asserted at the negation of HRESET, no-DRTRY mode is selected.
Bus Interface Operation | gx_08.fm.(1.2) |
Page 318 of 377 | March 27, 2006 |
