IBM 750GL, 750GX State, Note:, State, Timing, 7.2.6 Data-BusArbitration Signals, 7.2.6.1 Data-BusGrant (DBG)—Input

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Address Retry (ARTRY)—Input

State	Asserted	If the 750GX is the address-bus master, ARTRY indicates that the 750GX
		must retry the preceding address tenure and immediately negate BR (if
		asserted). If the associated data tenure has already started, the 750GX also
		cancels the data tenure immediately, even if the burst data has been
		received. If the 750GX is not the address-bus master, this input indicates
		that the 750GX should immediately negate BR to allow an opportunity for a
		copy-back operation to main memory after a snooping bus master asserts
		ARTRY. Note that the subsequent address presented on the address bus
		might not be the same one associated with the assertion of the ARTRY
		signal.
	Negated/	Indicates that the 750GX does not need to retry the last address tenure.
	High
	Impedance
Timing
	Assertion	May occur as early as the second cycle following the assertion of				TS,	and
		must occur by the bus clock cycle immediately following the assertion of
		AACK if an address retry is required.
	Negation/	Must occur the second cycle following the assertion of	AACK	(if	ARTRY			was
	High	asserted).
	Impedance

Note: During the second cycle following the assertion of AACK, ARTRY is first set to the high impedance state by the asserting masters, and might be sampled in an indeterminate state.

7.2.6 Data-Bus Arbitration Signals

Like the address-bus arbitration signals, data-bus arbitration signals maintain an orderly process for determining data-bus mastership. Note that there is no data-bus arbitration signal equivalent to the address-bus arbitration signal BR (bus request), because, except for address-only transactions, TS implies data-bus requests. For a detailed description of how these signals interact, see Section 8.4.1, Data-Bus Arbitration, on page 301.

One special signal, DBWO, allows the 750GX to be configured dynamically to write data out of order with respect to read data. For detailed information about using the DBWO, see Section 8.9, Using Data-Bus Write- Only, on page 320.

7.2.6.1 Data-Bus Grant (DBG)—Input

The data-bus grant (DBG) signal is an input-only signal on the 750GX.

State	Asserted	Indicates that the 750GX may, with proper qualification, assume mastership
		of the data bus. A qualified bus grant occurs when DBG is asserted and
		DBB, DRTRY, and ARTRY are not asserted. ARTRY is only for the address-
		bus tenure associated with the data-bus tenure about to be granted (that is,
		not from another address tenure due to address pipelining).
Signal Descriptions		gx_07.fm.(1.2)
Page 264 of 377		March 27, 2006