IBM 750GL, 750GX 5.1.7 MMU Exceptions Summary

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

If the T bit in the Segment Register is cleared (SR[T] = 0), then page-address translation is selected. The information in the segment descriptor is then used to generate the 52-bit virtual address. The virtual address is used to identify the page-address-translation information (stored as page table entries [PTEs] in a page table in memory). For increased performance, the 750GX has two on-chip TLBs to cache recently-used translations on-chip.

If an access hits in the appropriate TLB, page translation succeeds and the physical address bits are forwarded to the memory subsystem. If the required translation is not resident, the MMU performs a search of the page table. If the required PTE is found, a TLB entry is allocated and the page translation is attempted again. This time, the TLB is guaranteed to hit. When the translation is located, the access is qualified with the appropriate protection bits. If the access causes a protection violation, either an ISI or DSI exception is gener- ated.

If the PTE is not found by the table-search operation, a page-fault condition exists, and an ISI or DSI exception occurs so software can handle the page fault.

5.1.7 MMU Exceptions Summary

To complete any memory access, the effective address must be translated to a physical address. As specified by the architecture, an MMU exception condition occurs if this translation fails for one of the following reasons:

•Page fault. There is no valid entry in the page table for the page specified by the effective address (and segment descriptor), and there is no valid BAT translation.

•An address translation is found, but the access is not allowed by the memory-protection mechanism.

The translation exception conditions defined by the OEA for 32-bit implementations cause either the ISI or the DSI exception to be taken as shown in Table 5-3.

I

Table 5-3. Translation Exception Conditions (Page 1 of 2)

Condition	Description	Exception
		I access: ISI exception
Page fault (no PTE found)	No matching PTE found in page tables (and no matching	SRR1[1] = 1
	BAT array entry)	D access: DSI exception
		DSISR[1] =1
	Conditions described for blocks in “Block Memory Pro-	I access: ISI exception
		SRR1[4] = 1
Block protection violation	tection” in Chapter 7, “Memory Management,” in the
	PowerPC Microprocessor Family: The Programming	D access: DSI exception
	Environments Manual.“
		DSISR[4] =1
	Conditions described for pages in “Page Memory Protec-	I access: ISI exception
Page-protection violation	tion” in Chapter 7, “Memory Management,” in the Pow-	SRR1[4] = 1
	erPC Microprocessor Family: The Programming	D access: DSI exception
	Environments Manual.
		DSISR[4] = 1
No-execute protection violation	Attempt to fetch instruction when SR[N] = 1	ISI exception
		SRR1[3] = 1

Memory Management	gx_05.fm.(1.2)
Page 192 of 377	March 27, 2006