User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.3 Instruction Set Summary

This section describes instructions and addressing modes defined for the 750GX. These instructions are divided into the following functional categories:

Integer

These include arithmetic and logical instructions. For more information, see

 

Section 2.3.4.1 on page 92.

Floating-point

These include floating-point arithmetic instructions (single-precision and double-

 

precision), as well as instructions that affect the Floating-Point Status and Control

 

Register (FPSCR). For more information, see Section 2.3.4.2 on page 95.

Load and store

These include integer and floating-point (including quantized) load-and-store

 

instructions. For more information, see Section 2.3.4.3 on page 98.

Flow control

These include branching instructions, Condition Register logical instructions, trap

 

instructions, and other instructions that affect the instruction flow. For more infor-

 

mation, see Section 2.3.4.4 on page 106.

Processor control

These instructions are used for synchronizing memory accesses and managing

 

caches, translation lookaside buffers (TLBs), and Segment Registers. For more

 

information, see Section 2.3.4.6 on page 108, Section 2.3.5.1 on page 113, and

 

Section 2.3.6.2 on page 118.

Memory synchronization These instructions are used for memory synchronizing. For more information, see Section 2.3.4.7 on page 113 and Section 2.3.5.2 on page 114.

Memory control

These instructions provide control of caches, TLBs, and Segment Registers. For

 

more information, see Section 2.3.5.3 on page 115 and Section 2.3.6.3 on

 

page 119.

External control

These include instructions for use with special input/output devices. For more infor-

 

mation, see Section 2.3.5.4 on page 117.

Note: This grouping of instructions does not necessarily indicate the execution unit that processes a particular instruction or group of instructions. That information, which is useful for scheduling instructions most effec- tively, is provided in Chapter 6, Instruction Timing, on page 209.

Integer instructions operate on word operands. Floating-point instructions operate on single-precision and double-precision floating-point operands. The PowerPC Architecture uses instructions that are 4 bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 General Purpose Registers (GPRs). It provides for word and double-word operand loads and stores between memory and a set of 32 Floating Point Registers (FPRs).

Arithmetic and logical instructions do not read or modify memory. To use the contents of a memory location in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written to the target location using load-and-store instructions.

The description of each instruction beginning on page 92 includes the mnemonic and a formatted list of oper- ands. To simplify assembly language programming, a set of simplified mnemonics and symbols is provided for some of the frequently-used instructions; see Appendix F, “Simplified Mnemonics,” in the PowerPC Microprocessor Family: The Programming Environments Manual for a complete list of simplified mnemonics. Note

Programming Model

gx_02.fm.(1.2)

Page 86 of 377

March 27, 2006