User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 3-1. MEI State Definitions

MEI State

Definition

The addressed cache block is present in the cache, and is modified with respect to system memory. That is, the Modified (M) modified data in the cache block has not been written back to memory. The cache block might be present in

750GX’s L2 cache, but it is not present in any other coherent cache.

The addressed cache block is present in the cache, and this cache has exclusive ownership of the addressed Exclusive (E) block. The addressed block might be present in 750GX’s L2 cache, but it is not present in any other processor’s

Invalid (I)

cache. The data in this cache block is consistent with system memory.

This state indicates that the address block does not contain valid data, or that the addressed cache block is not resident in the cache.

The 750GX provides dedicated hardware to provide memory coherency by snooping bus transactions. Figure 3-4on page 128 shows the MEI cache-coherency protocol, as enforced by the 750GX. The information in this figure assumes that the WIM bits for the page or block are set to 001; that is, write-back, caching- not-inhibited, and memory coherency enforced.

Since data cannot be shared, the 750GX signals all cache block fills as if they were write misses (read-with- intent-to-modify), which flushes the corresponding copies of the data in all caches external to the 750GX prior to the cache-block-fill operation. Following the cache-block load, the 750GX is the exclusive owner of the data and can write to it without a bus broadcast transaction.

To maintain the 3-state coherency, all global reads observed on the bus by the 750GX are snooped as if they were writes, causing the 750GX to flush the cache block (write the cache block back to memory and invalidate the cache block if it is modified, or simply invalidate the cache block if it is unmodified). The exception to this rule occurs when a snooped transaction is a caching-inhibited read1, in which case the 750GX does not invalidate the snooped cache block. If the cache block is modified, the block is written back to memory, and the cache block is marked exclusive. If the cache block is marked exclusive, no bus action is taken, and the cache block remains in the exclusive state.

This treatment of caching-inhibited reads decreases the possibility of data thrashing by allowing noncaching devices to read data without invalidating the entry from the 750GX’s data cache.

1. Either burst or single-beat, where the transfer type (TT[0–4]) = X1010. See Table 7-1on page 256 for clarification.

gx_03.fm.(1.2)

Instruction-Cache and Data-Cache Operation

March 27, 2006

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