IBM 750GL, 750GX manual 8

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
6.6.1.3 Completion-Unit Resource Requirements ....................................................................	237
6.7 Instruction Latency Summary ........................................................................................................	238
7. Signal Descriptions .................................................................................................	249
7.1 Signal Configuration ......................................................................................................................	250
7.2 Signal Descriptions ........................................................................................................................	251
7.2.1 Address-Bus Arbitration Signals ..........................................................................................	251
7.2.1.1 Bus Request (BR)—Output ..........................................................................................	251
7.2.1.2 Bus Grant (BG)—Input .................................................................................................	252
7.2.1.3 Address Bus Busy (ABB) ..............................................................................................	252
7.2.2 Address Transfer Start Signals ............................................................................................	253
7.2.2.1 Transfer Start (TS) ........................................................................................................	253
7.2.3 Address Transfer Signals .....................................................................................................	254
7.2.3.1 Address Bus (A[0–31]) .................................................................................................	254
7.2.3.2 Address-Bus Parity (AP[0–3]) .......................................................................................	255
7.2.4 Address Transfer Attribute Signals ......................................................................................	255
7.2.4.1 Transfer Type (TT[0–4]) ...............................................................................................	256
7.2.4.2 Transfer Size (TSIZ[0–2])—Output ...............................................................................	258
7.2.4.3 Transfer Burst (TBST) ..................................................................................................	259
7.2.4.4 Cache Inhibit (CI)—Output ...........................................................................................	260
7.2.4.5 Write-Through(WT)—Output .......................................................................................	260
7.2.4.6 Global (GBL) .................................................................................................................	261
7.2.5 Address Transfer Termination Signals .................................................................................	262
7.2.5.1 Address Acknowledge (AACK)—Input .........................................................................	262
7.2.5.2 Address Retry (ARTRY) ...............................................................................................	263
7.2.6 Data-Bus Arbitration Signals ................................................................................................	264
7.2.6.1 Data-Bus Grant (DBG)—Input ......................................................................................	264
7.2.6.2 Data-BusWrite-Only (DBWO) ......................................................................................	265
7.2.6.3 Data Bus Busy (DBB) ...................................................................................................	265
7.2.7 Data-Transfer Signals ..........................................................................................................	266
7.2.7.1 Data Bus (DH[0–31],DL[0–31]) ....................................................................................	266
7.2.7.2 Data-Bus Parity (DP[0–7]) ............................................................................................	267
7.2.7.3 Data Bus Disable (DBDIS)—Input ................................................................................	268
7.2.8 Data-Transfer Termination Signals ......................................................................................	268
7.2.8.1 Transfer Acknowledge (TA)—Input ..............................................................................	268
7.2.8.2 Data Retry (DRTRY)—Input .........................................................................................	269
7.2.8.3 Transfer Error Acknowledge (TEA)—Input ...................................................................	269
7.2.9 System Status Signals .........................................................................................................	270
7.2.9.1 Interrupt (INT)— Input ..................................................................................................	270
7.2.9.2 System Management Interrupt (SMI)—Input ................................................................	270
7.2.9.3 Machine-Check Interrupt (MCP)—Input .......................................................................	271
7.2.9.4 Checkstop Input (CKSTP_IN)—Input ...........................................................................	271
7.2.9.5 Checkstop Output (CKSTP_OUT)—Output .................................................................	271
7.2.10 Reset Signals .....................................................................................................................	272
7.2.10.1 Hard Reset (HRESET)—Input ....................................................................................	272
7.2.10.2 Soft Reset (SRESET)—Input .....................................................................................	272
7.2.11 Processor Status Signals ...................................................................................................	273
7.2.11.1 Quiescent Request (QREQ)—Output .........................................................................	273
7.2.11.2 Quiescent Acknowledge (QACK)—Input ....................................................................	273
7.2.11.3 Reservation (RSRV)—Output .....................................................................................	273
	750gx_umTOC.fm.(1.2)
Page 8 of 377	March 27, 2006