IBM 750GL, 750GX 8.4.4.1 Normal Single-BeatTermination

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

(or only) data beat, the 750GX negates DBB but still considers the data beat active and waits for another assertion of TA. DRTRY is ignored on write operations. TEA indicates a nonrecoverable bus error event. Upon receiving a final (or only) termination condition, the 750GX always negates DBB for one cycle.

If DRTRY is asserted by the memory system to extend the last (or only) data beat past the negation of DBB, the memory system should tristate the data bus on the clock after the final assertion of TA, even though it will negate DRTRY on that clock. This is to prevent a potential momentary data-bus conflict if a write access begins on the following cycle.

The TEA signal is used to signal a nonrecoverable error during the data transaction. It can be asserted on any cycle during DBB, or on the cycle after a qualified TA during a read operation, except when no-DRTRY mode is selected (where no-DRTRY mode cancels checking the cycle after TA). The assertion of TEA terminates the data tenure immediately even if in the middle of a burst. However, it does not prevent incorrect data that has just been acknowledged with a TA from being written into the 750GX cache or to GPRs. The assertion of TEA initiates either a machine-check exception or a checkstop condition based on the setting of the MSR[ME] bit.

An assertion of ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the address tenure associated with the data tenure in operation. If ARTRY is connected for the 750GX, the earliest allowable assertion of TA to the 750GX is directly dependent on the earliest possible assertion of ARTRY to the 750GX; see Section 8.3.3, Address Transfer Termination, on page 300.

8.4.4.1 Normal Single-Beat Termination

Normal termination of a single-beat data read operation occurs when TA is asserted by a responding slave. The TEA and DRTRY signals must remain negated during the transfer (see Figure 8-11).

Figure 8-11. Normal Single-Beat Read Termination

0		1		2		3		4

TS

qual DBG

DBB

data

ta

drtry

AACK

The DRTRY signal is not sampled during data writes, as shown in Figure 8-12.

Bus Interface Operation	gx_08.fm.(1.2)
Page 304 of 377	March 27, 2006

Contents

Page Page List of Figures List of Tables About This Manual Page 3. Instruction-Cacheand Data-CacheOperation 4. Exceptions Page 6. Instruction Timing Page 8. Bus Interface Operation 10. Power and Thermal Management 11. Performance Monitor and System Related Features Acronyms and Abbreviations Index Revision Log Page List of Figures Page List of Tables Page Page Page About This Manual Who Should Read This Manual Related Publications Conventions Used in This Manual Terminology Conventions Instruction Field Conventions Using This Manual with the Programming Environments Manual 1. PowerPC 750GX Overview 1.1 750GX Microprocessor Overview Page 1.2 750GX Microprocessor Features Page Page Page 1.2.1 Instruction Flow 1.2.1.1 Instruction Queue and Dispatch Unit 1.2.1.2 Branch Processing Unit (BPU) bclr 1.2.1.3 Completion Unit 1.2.2 Independent Execution Units 1.2.2.1 Integer Units (IUs) 1.2.2.2 Floating-PointUnit (FPU) 1.2.2.3 Load/Store Unit (LSU) 1.2.2.4 System Register Unit (SRU) 1.2.3 Memory Management Units (MMUs) 1.2.4 On-ChipLevel 1 Instruction and Data Caches Page 1.2.5 On-ChipLevel 2 Cache Implementation 1.2.6 System Interface/Bus Interface Unit (BIU) Page 1.2.7 Signals Note 1.2.8 Signal Configuration Page 1.3 750GX Microprocessor Implementation Page 1.4 PowerPC Registers and Programming Model Page Page 1.5 Instruction Set Page 1.6 On-ChipCache Implementation 1.7 Exception Model 1.7.2 750GX Microprocessor Exception Implementation Page 1.8 Memory Management 1.9 Instruction Timing Page 1.10 Power Management 1.11 Thermal Management 1.12 Performance Monitor 2. Programming Model 2.1 PowerPC 750GX Processor Register Set Page Implementation Note: User-level registers Implementation Note lscbx Supervisor-level Page -specific Page 2.1.2 PowerPC 750GX-SpecificRegisters 2.1.2.1 Instruction Address Breakpoint Register (IABR) 2.1.2.2 Hardware-Implementation-DependentRegister 0 (HID0) Page Page Page Page 2.1.2.3 Hardware-Implementation-DependentRegister 1 (HID1) 2.1.2.4 Hardware-Implementation-DependentRegister 2 (HID2) 2.1.2.5 Performance-MonitorRegisters Page Page Page Page 2.1.3 Instruction Cache Throttling Control Register (ICTC) 2.1.4 Thermal-ManagementRegisters (THRMn) 2.1.4.1 Thermal-ManagementRegisters 1–2 (THRM1–THRM2) 2.1.4.2 Thermal-ManagementRegister 3 (THRM3) 2.1.4.3 Thermal-ManagementRegister 4 (THRM4) 2.1.5 L2 Cache Control Register (L2CR) 2.2 Operand Conventions 2.2.3 Floating-PointOperand and Execution Models—UISA 2.2.3.1 Denormalized Number Support 2.2.3.2 Non-IEEEMode (Nondenormalized Mode) 2.2.3.3 Time-Critical Floating-PointOperation 2.2.3.4 Floating-PointStorage Access Alignment 2.2.3.5 Optional Floating-PointGraphics Instructions fsel(.) fres(.) Page 2.3 Instruction Set Summary 2.3.1 Classes of Instructions 2.3.1.1 Definition of Boundedly Undefined 2.3.1.2 Defined Instruction Class fsqrt fsqrts 2.3.1.3 Illegal Instruction Class 2.3.1.4 Reserved Instruction Class 2.3.2 Addressing Modes 2.3.2.1 Memory Addressing 2.3.2.2 Memory Operands 2.3.2.3 Effective Address Calculation 2.3.2.4 Synchronization mfsrin) mtsrin 2.3.3 Instruction Set Overview 2.3.4 PowerPC UISA Instructions 2.3.4.1 Integer Instructions addi subf cmpi cmp cmpli andi andis 2.3.4.2 Floating-PointInstructions fmul fmadd fmsub fnmadd fnmsub Page mtfsf 2.3.4.3 Load-and-StoreInstructions Page Implementation Notes lha lhax lbzu Page eieio) Implementation Notes: Page lfsx lfsux lfdx lfdux Programming Note: Page stfsu stfdu 2.3.4.4 Branch and Flow-ControlInstructions bla bca Page 2.3.4.5 System Linkage Instruction—UISA 2.3.4.6 Processor Control Instructions—UISA mtcrf Page Page Page 2.3.4.7 Memory Synchronization Instructions—UISA 2.3.5 PowerPC VEA Instructions 2.3.5.1 Processor Control Instructions—VEA mftbu 2.3.5.2 Memory Synchronization Instructions—VEA 2.3.5.3 Memory Control Instructions—VEA Page 2.3.5.4 Optional External Control Instructions 2.3.6 PowerPC OEA Instructions 2.3.6.1 System Linkage Instructions—OEA 2.3.6.2 Processor Control Instructions—OEA 2.3.6.3 Memory Control Instructions—OEA tlbia 2.3.7 Recommended Simplified Mnemonics 3. Instruction-Cacheand Data-CacheOperation Page 3.1 Data-CacheOrganization 3.2 Instruction-CacheOrganization 3.3 Memory and Cache Coherency mtspr) 3.3.2 MEI Protocol Page 3.3.2.1 MEI Hardware Considerations 3.3.3 Coherency Precautions in Single-ProcessorSystems 3.3.4 Coherency Precautions in Multiprocessor Systems 3.3.5 PowerPC 750GX-InitiatedLoad/Store Operations 3.3.5.1 Performed Loads and Stores 3.3.5.2 Sequential Consistency of Memory Accesses 3.3.5.3 Atomic Memory References 3.4 Cache Control 3.4.1.1 Data-CacheFlash Invalidation 3.4.1.2 Enabling and Disabling the Data Cache dcbz) dcbf) 3.4.1.3 Locking the Data Cache 3.4.1.4 Instruction-CacheFlash Invalidation 3.4.1.5 Enabling and Disabling the Instruction Cache 3.4.1.6 Locking the Instruction Cache 3.4.2 Cache-ControlInstructions 3.4.2.2 Data Cache Block Zero (dcbz) 3.4.2.3 Data Cache Block Store (dcbst) 3.4.2.4 Data Cache Block Flush (dcbf) 3.4.2.5 Data Cache Block Invalidate (dcbi) 3.5 Cache Operations Page 3.5.2 Cache Flush Operations 3.6 L1 Caches and 60x Bus Transactions 3.6.1 Read Operations and the MEI Protocol 3.6.2 Bus Operations Caused by Cache-ControlInstructions 3.6.3 Snooping 3.6.4 Snoop Response to 60x Bus Transactions Page 3.6.5 Transfer Attributes Page 3.7 MEI State Transactions Page Page Page 4. Exceptions 4.1 PowerPC 750GX Microprocessor Exceptions 4.2 Exception Recognition and Priorities Page Page 4.3 Exception Processing 4.3.2 Machine Status Save/Restore Register 1 (SRR1) 4.3.3 Machine State Register (MSR) Page 4.3.4 Enabling and Disabling Exceptions 4.3.5 Steps for Exception Processing 4.3.6 Setting MSR[RI] 4.3.7 Returning from an Exception Handler 4.4 Process Switching 4.5 Exception Definitions 4.5.1 System Reset Exception (0x00100) 4.5.1.1 Soft Reset 4.5.1.2 Hard Reset Page Page 4.5.2 Machine-CheckException (0x00200) 4.5.2.1 Machine-CheckException Enabled (MSR[ME] = 1) 4.5.2.2 Checkstop State (MSR[ME] = 0) 4.5.3 DSI Exception (0x00300) 4.5.4 ISI Exception (0x00400) 4.5.5 External Interrupt Exception (0x00500) 4.5.6 Alignment Exception (0x00600) stmw 4.5.7 Program Exception (0x00700) 4.5.8 Floating-PointUnavailable Exception (0x00800) 4.5.9 Decrementer Exception (0x00900) 4.5.10 System Call Exception (0x00C00) 4.5.11 Trace Exception (0x00D00) 4.5.12 Floating-PointAssist Exception (0x00E00) 4.5.13 Performance-MonitorInterrupt (0x00F00) 4.5.14 Instruction Address Breakpoint Exception (0x01300) 4.5.15 System Management Interrupt (0x01400) 4.5.16 Thermal-ManagementInterrupt Exception (0x01700) 4.5.17 Data Address Breakpoint Exception 4.5.17.1 Data Address Breakpoint Register (DABR) 4.5.18 Soft Stops 4.5.19 Exception Latencies 4.5.20 Summary of Front-EndException Handling 4.5.21 Timer Facilities 4.5.22 External Access Instructions Page 5. Memory Management 5.1 MMU Overview Page 5.1.1 Memory Addressing 5.1.2 MMU Organization Page Page Page Page 5.1.3 Address-TranslationMechanisms 5.1.4 Memory-ProtectionFacilities 5.1.5 Page History Information 5.1.6 General Flow of MMU Address Translation 5.1.6.1 Real-AddressingMode and Block-Address-TranslationSelection 5.1.6.2 Page-Address-TranslationSelection Page 5.1.7 MMU Exceptions Summary Notes: 5.1.8 MMU Instructions and Register Summary 5.2 Real-AddressingMode 5.3 Block-AddressTranslation 5.4 Memory Segment Model 5.4.1.1 Referenced Bit lswx 5.4.1.2 Changed Bit 5.4.1.3 Scenarios for Referenced and Changed Bit Recording 5.4.2 Page Memory Protection 5.4.3 TLB Description 5.4.3.1 TLB Organization Page 5.4.3.2 TLB Invalidation 5.4.4 Page-Address-TranslationSummary Page 5.4.5 Page Table-SearchOperation Page Page 5.4.6 Page Table Updates 5.4.7 Segment Register Updates Page 6. Instruction Timing 6.1 Terminology and Conventions Page 6.2 Instruction Timing Overview Page Page Page 6.3 Timing Considerations 6.3.2 Instruction Fetch Timing 6.3.2.1 Cache Arbitration 6.3.2.2 Cache Hit Page Page Page Page 6.3.2.3 Cache Miss Page 6.3.2.4 L2 Cache Access Timing Considerations 6.3.2.5 Instruction Dispatch and Completion Considerations 6.3.2.6 Rename Register Operation 6.4 Execution-UnitTimings 6.4.1.1 Branch Folding 6.4.1.2 Branch Instructions and Completion 6.4.1.3 Branch Prediction and Resolution Page Page mulhw 6.4.2 Integer Unit Execution Timing 6.4.3 Floating-PointUnit Execution Timing fdivs fdiv mtfsb0 6.4.5 Load/Store Unit Execution Timing 6.4.6 Effect of Operand Placement on Performance 6.4.7 Integer Store Gathering 6.4.8 System Register Unit Execution Timing 6.5 Memory Performance Considerations 6.6 Instruction Scheduling Guidelines 6.6.1 Branch, Dispatch, and Completion-UnitResource Requirements 6.6.1.1 Branch-ResolutionResource Requirements 6.6.1.2 Dispatch-UnitResource Requirements 6.6.1.3 Completion-UnitResource Requirements 6.7 Instruction Latency Summary Page Page Page Page Page Page Page Page Page Page 7. Signal Descriptions 7.1 Signal Configuration 7.2 Signal Descriptions 7.2.1.2 Bus Grant (BG)—Input 7.2.1.3 Address Bus Busy (ABB) 7.2.2 Address Transfer Start Signals 7.2.2.1 Transfer Start (TS) 7.2.3 Address Transfer Signals 7.2.3.1 Address Bus (A[0–31]) 7.2.3.2 Address-BusParity (AP[0–3]) 7.2.4 Address Transfer Attribute Signals 7.2.4.1 Transfer Type (TT[0–4]) Page 7.2.4.2 Transfer Size (TSIZ[0–2])—Output 7.2.4.3 Transfer Burst (TBST) 7.2.4.4 Cache Inhibit (CI)—Output 7.2.4.5 Write-Through (WT)—Output 7.2.4.6 Global (GBL) 7.2.5 Address Transfer Termination Signals 7.2.5.1 Address Acknowledge (AACK)—Input 7.2.5.2 Address Retry (ARTRY) 7.2.6 Data-BusArbitration Signals 7.2.6.1 Data-BusGrant (DBG)—Input 7.2.6.2 Data-Bus Write-Only(DBWO) 7.2.6.3 Data Bus Busy (DBB) 7.2.7 Data-TransferSignals 7.2.7.1 Data Bus (DH[0–31], DL[0–31]) 7.2.7.2 Data-BusParity (DP[0–7]) 7.2.7.3 Data Bus Disable (DBDIS)—Input 7.2.8 Data-TransferTermination Signals 7.2.8.1 Transfer Acknowledge (TA)—Input Warning 7.2.8.2 Data Retry (DRTRY)—Input 7.2.8.3 Transfer Error Acknowledge (TEA)—Input 7.2.9 System Status Signals 7.2.9.1 Interrupt (INT)— Input 7.2.9.2 System Management Interrupt (SMI)—Input 7.2.9.3 Machine-CheckInterrupt (MCP)—Input 7.2.9.4 Checkstop Input (CKSTP_IN)—Input 7.2.9.5 Checkstop Output (CKSTP_OUT)—Output 7.2.10 Reset Signals 7.2.10.1 Hard Reset (HRESET)—Input 7.2.10.2 Soft Reset (SRESET)—Input 7.2.11 Processor Status Signals 7.2.11.1 Quiescent Request (QREQ)—Output 7.2.11.2 Quiescent Acknowledge (QACK)—Input 7.2.11.3 Reservation (RSRV)—Output 7.2.11.4 Time Base Enable (TBEN)—Input 7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)—Input 7.2.12 Processor Mode Selection Signals 7.2.13 I/O Voltage Select Signals 7.2.14 Test Interface Signals 7.2.14.1 IEEE 1149.1a-1993Interface Description 7.2.14.2 LSSD_MODE 7.2.14.3 L1_TSTCLK 7.2.14.4 L2_TSTCLK 7.2.14.5 BVSEL 7.2.15 Clock Signals 7.2.15.1 System Clock (SYSCLK)—Input 7.2.15.2 Clock Out (CLK_OUT)—Output 7.2.15.3 PLL Configuration (PLL_CFG[0:4])—Input 7.2.15.4 PLL Range (PLL_RNG[0:1])—Input 7.2.16 Power and Ground Signals 8. Bus Interface Operation 8.1 Bus Interface Overview 8.1.1 Operation of the Instruction and Data L1 Caches 8.1.2 Operation of the Bus Interface 8.1.3 Bus Signal Clocking System Implementation Note: 8.1.4 Optional 32-BitData Bus Mode 8.1.5 Direct-StoreAccesses 8.2 Memory-AccessProtocol 8.2.1 Arbitration Signals 8.2.2 Miss-under-Miss 8.2.2.1 Miss-under-Missand System Performance Page Page 8.3 Address-BusTenure Page 8.3.2 Address Transfer Page 8.3.2.1 Address-BusParity 8.3.2.2 Address Transfer Attribute Signals 8.3.2.3 Burst Ordering During Data Transfers 8.3.2.4 Effect of Alignment in Data Transfers Page Page Page 8.3.2.5 Alignment of External Control Instructions 8.3.3 Address Transfer Termination 8.4 Data-BusTenure 8.4.1.1 Using the DBB Signal 8.4.2 Data-Bus Write-Only 8.4.3 Data Transfer 8.4.4 Data-TransferTermination 8.4.4.1 Normal Single-BeatTermination Page Page 8.4.4.2 Data-TransferTermination Due to a Bus Error 8.4.5 Memory Coherency—MEIProtocol 8.5 Timing Examples Page Page Page Page Page Page 8.6 Optional Bus Configuration Page 8.6.2 No-DRTRYMode 8.7 Processor State Signals 8.8 IEEE 1149.1a-1993Compliant Interface 8.9 Using Data-Bus Write-Only Page Page 9. L2 Cache 9.1 L2 Cache Overview 9.2 L2 Cache Operation Page Page Page Page dcbst) dcbi) sync) 9.3 L2 Cache Control Register (L2CR) 9.4 L2 Cache Initialization 9.5 L2 Cache Global Invalidation 9.6 L2 Cache Used as On-ChipMemory 9.6.1.1 Loading the Locked L2 Cache 9.6.1.2 Locked Cache Operation 9.7 Data-Onlyand Instruction-OnlyModes 9.8 L2 Cache Test Features and Methods 9.9 L2 Cache Timing Page 10. Power and Thermal Management 10.1 Dynamic Power Management 10.2 Programmable Power Modes Page 10.2.1 Power Management Modes 10.2.1.1 Full On Mode 10.2.1.2 Doze Mode 10.2.1.3 Nap Mode Page 10.2.1.4 Sleep Mode 10.2.1.5 Dynamic Power Reduction 10.3 750GX Dual PLL Feature 10.3.2 Configuration Restriction on Frequency Transitions 10.3.3 Dual PLL Implementation 10.4 Thermal Assist Unit 10.4.2 Thermal Assist Unit Operation 10.4.2.1 TAU Single-ThresholdMode 10.4.2.2 TAU Dual-ThresholdMode 10.4.2.3 750GX Junction Temperature Determination 10.5 Instruction-CacheThrottling Page 11. Performance Monitor and System Related Features 11.1 Performance-MonitorInterrupt 11.2 Special-PurposeRegisters Used by Performance Monitor 11.2.1 Performance-MonitorRegisters 11.2.1.1 Monitor Mode Control Register 0 (MMCR0) 11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0) 11.2.1.3 Monitor Mode Control Register 1 (MMCR1) 11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1) Page Page 11.2.1.6 User Performance-MonitorCounter Registers (UPMC1–UPMC4) 11.3 Event Counting 11.4 Event Selection 11.5 Notes 11.6 Debug Support 11.7 JTAG/COP Functions Page 11.8 Resets 11.8.3 Reset Sequence 11.9 Checkstops 11.9.3 Open-Collector-DriverStates during Checkstop 11.9.4 Vacancy Slot Application 11.10 750GX Parity 11.10.1 Parity Control and Status 11.10.2 Enabling Parity Error Detection 11.10.3 Parity Errors Acronyms and Abbreviations Page Page Page Index Page H, I, J, K Page Page Page U, V, W Page Revision Log