User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Integer Load-and-Store String Instructions

The integer load-and-store string instructions allow movement of data from memory to registers, or from registers to memory, without concern for alignment. These instructions can be used for a short move between arbitrary memory locations or to initiate a long move between misaligned memory fields. However, in some implementations, these instructions are likely to have greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results.

Table 2-20summarizes the integer load-and-store string instructions. In other PowerPC implementations operating with little-endian byte order, execution of a load or string instruction invokes the alignment error handler. See “Byte Ordering” in the PowerPC Microprocessor Family: The Programming Environments Manual for more information.

Table 2-22. Integer Load-and-Store String Instructions

Name

Mnemonic

Syntax

 

 

 

 

 

 

Load String Word Immediate

lswi

rD,rA,NB

 

 

 

Load String Word Indexed

lswx

rD,rA,rB

 

 

 

Store String Word Immediate

stswi

rS,rA,NB

 

 

 

Store String Word Indexed

stswx

rS,rA,rB

 

 

 

Load string and store string instructions might involve operands that are not word-aligned.

As described in Section 4.5.6 on page 170, a misaligned string operation suffers a performance penalty compared to an aligned operation of the same type.

Anon-word-aligned string operation that crosses a 4-KB boundary, or a word-aligned string operation that crosses a 256-MB boundary, always causes an alignment exception. A non-word-aligned string operation that crosses a double-word boundary is also slower than a word-aligned string operation.

Implementation Notes: The following describes the 750GX implementation of load/store string instructions:

•For load/store string operations, the hardware does not combine register values to reduce the number of discrete accesses. However, if store gathering is enabled and the accesses fall under the criteria for store gathering, the stores can be combined to enhance performance. At a minimum, additional cache access cycles are required.

•The 750GX supports misaligned, single-register load-and-store accesses in little-endian mode without causing an alignment exception. However, execution of misaligned load/store multiple/string operations causes an alignment exception.

Floating-Point Load-and-Store Address Generation

Floating-point load-and-store operations generate effective addresses using the register indirect with immediate index addressing mode and register indirect with index addressing mode. Floating-point loads and stores are not supported for direct-store accesses. The use of floating-point loads and stores for direct-store access results in an alignment exception.

Implementation Notes: The 750GX treats exceptions as follows:

•The FPU can be run in two different modes—ignore-exceptions mode (MSR[FE0] = MSR[FE1] = 0) and precise-exception mode (any other settings for MSR[FE0,FE1]). For the 750GX, ignore-exceptions mode allows floating-point instructions to complete earlier and, thus, might provide better performance than pre- cise mode.

gx_02.fm.(1.2)

Programming Model

March 27, 2006

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