IBM 750GL, 750GX manual 105

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor Table 2-24summarizes the single-precision and double-precisionfloating-point store and stfiwx instructions.

Table 2-24. Floating-Point Store Instructions

Name	Mnemonic	Syntax
Store Floating-Point Single	stfs	frS,d(rA)
Store Floating-Point Single Indexed	stfsx	frS,rB
Store Floating-Point Single with Update	stfsu	frS,d(rA)
Store Floating-Point Single with Update Indexed	stfsux	frS,rB
Store Floating-Point Double	stfd	frS,d(rA)
Store Floating-Point Double Indexed	stfdx	frS,rB
Store Floating-Point Double with Update	stfdu	frS,d(rA)
Store Floating-Point Double with Update Indexed	stfdux	frS,rB
Store Floating-Point as Integer Word Indexed 1	stfiwx	frS,rB
1. The stfiwx instruction is optional in the PowerPC Architecture.

Some floating-point store instructions require conversions in the LSU. Table 2-25shows conversions the LSU makes when executing a Store Floating-Point Single instruction.

Table 2-25. Store Floating-Point Single Behavior

FPR Precision		Data Type	Action
Single		Normalized	Store
Single		Denormalized	Store
Single	Zero, infinity, QNaN		Store
Single		SNaN	Store
			If (exp ð ≤ 896)
Double		Normalized	then Denormalize and Store
			else
			Store
Double		Denormalized	Store zero
Double	Zero, infinity, QNaN		Store
Double		SNaN	Store

Note: The FPRs are not initialized by HRESET, and they must be initialized with some valid value after POR HRESET and before being stored.

Table 2-26shows the conversions made when performing a Store Floating-Point Double instruction. Most entries in the table indicate that the floating-point value is simply stored. Only in a few cases are any other actions taken.

Table 2-26. Store Floating-Point Double Behavior (Page 1 of 2)

FPR Precision	Data Type	Action
Single	Normalized	Store
Single	Denormalized	Normalize and Store
Single	Zero, infinity, QNaN	Store
gx_02.fm.(1.2)		Programming Model
March 27, 2006		Page 105 of 377