User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
10.2.1 Power Management ModesThe following sections describe the characteristics of the 750GX’s power management modes, the requirements for entering and exiting the various modes, and the system capabilities provided by the 750GX while the power management modes are active.
A power saving mode is activated by setting the power management enable bit in the Machine State Register (MSR[POW]) and one of the three HID0 power saving mode bits which are listed in Table
Table
HID0 Bits | Power Saving Mode |
8
9
10
Full on mode is selected when the POW bit in MSR is cleared. This is the default state following initialization of a hard reset (HRESET). The 750GX is fully powered, and all functional units are operating at full processor speed at all times.
10.2.1.2 Doze ModeDoze mode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping. A snoop hit causes the 750GX to enable the data cache, copy the data back to memory, disable the cache, and fully return to the doze state. Doze mode can be summarized as follows:
•Most functional units are disabled.
•Data cache, L2 cache, bus snooping logic, and the time base/decrementer are still enabled.
•Doze mode is enabled with the following sequence:
1.Set the doze bit (HID0[8] = 1); clear the nap and sleep bits (HID0[9] and HID0[10] = 0).
2.750GX enters doze mode after several processor clocks.
•Several methods of returning to
–Assert INT, MCP, SMI, decrementer,
–Assert hard reset or soft reset.
•Transition to
•
The nap mode disables the 750GX but still maintains the PLL and the time base/decrementer. The time base can be used to restore the 750GX to
gx_10.fm.(1.2) | Power and Thermal Management |
March 27, 2006 | Page 337 of 377 |