User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
8.6.2 No-DRTRY Mode .................................................................................................................
318
8.7
Processor State Signals ................................................................................................................
319
8.7.1 Support for the lwarx and stwcx. Instruction Pair ...............................................................
8.7.2 TLBISYNC Input ..................................................................................................................
8.8
IEEE 1149.1a-1993 Compliant Interface .......................................................................................
8.8.1 JTAG/COP Interface ............................................................................................................
8.9
Using Data-BusWrite-Only ...........................................................................................................
320
9. L2 Cache ...................................................................................................................
323
9.1
L2 Cache Overview .......................................................................................................................
9.2
L2 Cache Operation ......................................................................................................................
9.3
L2 Cache Control Register (L2CR) ...............................................................................................
329
9.4
L2 Cache Initialization ...................................................................................................................
9.5
L2 Cache Global Invalidation ........................................................................................................
9.6
L2 Cache Used as On-Chip Memory ............................................................................................
330
9.6.1 Locking the L2 Cache ..........................................................................................................
9.6.1.1 Loading the Locked L2 Cache ......................................................................................
331
9.6.1.2 Locked Cache Operation ..............................................................................................
9.7
Data-Only and Instruction-Only Modes .........................................................................................
332
9.8
L2 Cache Test Features and Methods ..........................................................................................
9.8.1 L2CR Support for L2 Cache Testing ....................................................................................
9.8.2 L2 Cache Testing .................................................................................................................
333
9.9
L2 Cache Timing ...........................................................................................................................
335
10.1 Dynamic Power Management .....................................................................................................
10.2 Programmable Power Modes ......................................................................................................
10.2.1 Power Management Modes ...............................................................................................
337
10.2.1.1 Full On Mode ..............................................................................................................
10.2.1.2 Doze Mode .................................................................................................................
10.2.1.3 Nap Mode ...................................................................................................................
10.2.1.4 Sleep Mode ................................................................................................................
339
10.2.1.5 Dynamic Power Reduction .........................................................................................
10.2.2 Power Management Software Considerations ...................................................................
340
10.3 750GX Dual PLL Feature ............................................................................................................
10.3.1 Overview ............................................................................................................................
10.3.2 Configuration Restriction on Frequency Transitions ..........................................................
341
10.3.3 Dual PLL Implementation ...................................................................................................
342
10.4 Thermal Assist Unit .....................................................................................................................
343
10.4.1 Thermal Assist Unit Overview ............................................................................................
10.4.2 Thermal Assist Unit Operation ...........................................................................................
344
10.4.2.1 TAU Single-Threshold Mode ......................................................................................
345
10.4.2.2 TAU Dual-Threshold Mode .........................................................................................
346
10.4.2.3 750GX Junction Temperature Determination .............................................................
10.4.2.4 Power Saving Modes and TAU Operation ..................................................................
347
10.5 Instruction-Cache Throttling ........................................................................................................
349
750gx_umTOC.fm.(1.2)
Page 10 of 377
March 27, 2006