IBM 750GL, 750GX 4.5.1 System Reset Exception (0x00100)

User’s Manual

IBM PowerPC 750GX and GL RISC Microprocessor

Table 4-5. MSR Setting Due to Exception (Page 2 of 2)

	Exception Type								MSR Bit2
		POW	ILE	EE	PR	FP	ME	FE0		SE	BE	FE1	IP	IR	DR	PM	RI	LE
System management		0	—	0	0	0	—	0		0	0	0	—	0	0	0	0	ILE
Performance monitor		0	—	0	0	0	—	0		0	0	0	—	0	0	0	0	ILE
Thermal management		0	—	0	0	0	—	0		0	0	0	—	0	0	0	0	ILE
Note:
1.	A zero indicates that the bit is cleared.
2.	The ILE bit is copied from the MSR[ILE].
3.	A dash indicates that the bit is not altered.
4.	Reserved bits are read as if written as 0.

The setting of the exception prefix bit (IP) determines how exceptions are vectored. If the bit is cleared, exceptions are vectored to the physical address 0x000n_nnnn (where nnnnn is the vector offset). If IP is set, exceptions are vectored to physical address 0xFFFn_nnnn. Table 4-2on page 152 shows the exception vector offset of the first instruction of the exception handler routine for each exception type.

4.5.1 System Reset Exception (0x00100)

The 750GX implements the system reset exception as defined in the PowerPC Architecture (OEA). The system reset exception is a nonmaskable, asynchronous exception signaled to the processor through the assertion of system-defined signals. In the 750GX, the exception is signaled by the assertion of either the soft reset (SRESET) or hard reset (HRESET) inputs, described more fully in Chapter 7, Signal Descriptions, on page 249

The 750GX implements HID0[NHR], which helps software distinguish a hard reset from a soft reset. Because this bit is cleared by a hard reset, but not by a soft reset, software can set this bit after a hard reset and tell whether a subsequent reset is a hard or soft reset by examining whether this bit is still set.

The first bus operation following the negation of HRESET or the assertion of SRESET will be a single-beat instruction fetch (caching will be inhibited) to x00100.

Table 4-6lists register settings when a system reset exception is taken.

Table 4-6. System Reset Exception–Register Settings

Register					Setting Description
SRR0	Set to the effective address of the instruction that the processor would have attempted to execute next if no exception
	conditions were present.
	0	Loaded with equivalent MSR bits
	1:4	Cleared
	5:9	Loaded with equivalent MSR bits
SRR1	10:15	Cleared
	16:31	Loaded with equivalent MSR bits
	Note: If the processor state is corrupted to the extent that execution cannot resume reliably, MSR[RI] (SRR1[30]) is
	cleared.
	POW	0	FP	0		BE	0	DR	0
MSR	ILE	—	ME	—		FE1	0	PM	0
	EE	0	FE0	0		IP	—	RI	0
	PR	0	SE	0		IR	0	LE	Set to value of ILE
gx_04.fm.(1.2)									Exceptions
March 27, 2006									Page 163 of 377