User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

7.2.4.1 Transfer Type (TT[0–4])

The transfer type (TT[0–4]) signals consist of five input/output signals on the 750GX. For a complete description of TT[0–4] signals and for transfer type encodings, see Table 7-1.

Transfer Type (TT[0–4])—Output

State

Asserted/

Indicates the type of transfer in progress.

 

Negated

 

Timing

Assertion/

The same as A[0–31].

 

Negation/

 

 

High

 

 

Impedance

 

Transfer Type (TT[0–4])—Input

 

State

Asserted/

Indicates the type of transfer in progress (see Table 7-1).

 

Negated

 

Timing

Assertion/

The same as A[0–31].

 

Negation

 

Table 7-1describes the transfer encodings for the 750GX bus master.

Table 7-1. Transfer Type Encodings for PowerPC 750GX Bus Master (Page 1 of 2)

750GX Bus

Transaction Source

TT0

TT1

TT2

TT3

TT4

60x Bus Specification

Transaction

Master Transaction

Command

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address only1

Data Cache Block Store

0

0

0

0

0

Clean block

Address only

(dcbst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address only1

Data Cache Block Flush

0

0

1

0

0

Flush block

Address only

(dcbf)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address only1

Synchronize (sync)

0

1

0

0

0

sync

Address only

Address only

Data Cache Block Set

0

1

1

0

0

Kill block

Address only

to Zero (dcbz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address only1

Data Cache Block Inval-

0

1

1

0

0

Kill block

Address only

idate (dcbi)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address only1

Enforce In-Order Exe-

1

0

0

0

0

eieio

Address only

cution of I/O (eieio)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Single-beat write

External Control Out

1

0

1

0

0

External control word write

Single-beat write

(nonGBL)

Word Indexed (ecowx)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N/A

N/A

1

1

0

0

0

Translation Lookaside Buffer

Address only

 

 

 

 

 

 

 

(TLB) invalidate

 

 

 

 

 

 

 

 

 

 

Single-beat read

External Control In

1

1

1

0

0

External control word read

Single-beat read

(nonGBL)

Word Indexed (eciwx)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. Address-only transaction occurs if enabled by setting the HID0[ABE] bit to 1.

Signal Descriptions

gx_07.fm.(1.2)

Page 256 of 377

March 27, 2006