User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Figure
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| Branch Folding |
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| Branch Folding |
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| (Taken Branch/BTIC Hit) |
| (Taken Branch/BTIC Miss) |
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| Clock 0 |
| Clock 1 | Clock 2 |
| Clock 0 | Clock 1 | Clock 2 |
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IQ5 |
| add5 |
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| IQ5 | add5 |
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IQ4 |
| add4 |
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| IQ4 | add4 |
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IQ3 |
| add3 |
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| and6 |
| IQ3 | add3 |
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| and4 |
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IQ2 |
| b |
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| and5 |
| IQ2 | b |
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| and3 |
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IQ1 |
| add2 |
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| and2 |
| and4 |
| IQ1 | add2 |
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| and2 |
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IQ0 | add1 |
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| and1 |
| and3 |
| IQ0 | add1 |
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| and1 |
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Figure
Figure
Branch
| Clock 0 | Clock 1 | Clock 2 | ||
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IQ5 | add5 |
| add8 |
| etc. |
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IQ4 | add4 |
| add7 |
| add9 |
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IQ3 | add3 |
| add6 |
| add8 |
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IQ2 | b |
| add5 |
| add7 |
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IQ1 | add2 |
| add4 |
| add6 |
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IQ0 | add1 |
| add3 |
| add5 |
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When a branch instruction is detected before it reaches a dispatch position, and if the branch is correctly predicted as taken, folding the branch instruction (and any instructions from the incorrect path) reduces the latency required for flow control to zero. Instruction execution proceeds as though the branch was never there.
The advantage of removing the
As described in the previous section, instructions that do not update either the LR or CTR are removed from the instruction stream before they reach the completion queue, either for branch taken or by removing fall- through branch instructions at dispatch. However, branch instructions that update the architected LR and CTR must do so in program order. Therefore, they must perform
Branch instructions that update the CTR or LR pass through the instruction queue like nonbranch instruc- tions. At the point of dispatch, however, they are not sent to an execution unit, but rather are assigned a slot in the completion queue, as shown in Figure
gx_06.fm.(1.2) | Instruction Timing |
March 27, 2006 | Page 227 of 377 |