User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

–Retires as many as two instructions per clock.

•Separate on-chip L1 instruction and data caches (Harvard architecture).

–32-KB, 8-way set-associative instruction and data caches.

–Pseudo least-recently-used (PLRU) replacement algorithm.

–32-byte (8-word) cache block.

–Physically indexed/physical tags.

Note: The PowerPC Architecture refers to physical address space as real address space.

–Cache write-back or write-through operation programmable on a virtual-page or BAT-block basis.

–Instruction cache can provide four instructions per clock; data cache can provide two words per clock

–Caches can be disabled in software.

–Caches can be locked in software.

–Data-cache coherency (MEI) maintained in hardware.

–The critical double word is made available to the requesting unit when it is read into the line-fill buffer. The cache is nonblocking, so it can be accessed during block reload.

–Nonblocking instruction cache (one outstanding miss).

–Nonblocking data cache (four outstanding misses).

–No snooping of instruction cache.

–Parity for L1 tags and caches.

•Integrated L2 cache.

–1-MB on-chip ECC SRAMs.

–On-chip 4-way set-associative tag memory.

–ECC error correction for most single-bit errors; detection of remaining single-bit errors and all double- bit errors.

–Copy-back or write-through data cache on a page basis, or for entire L2.

–64-byte line size, two sectors per line.

–L2 frequency at core speed.

–On-board ECC; parity for L2 tags.

–Supports up to four outstanding misses (three data and one instruction or four data).

–Cache locking by way.

•Separate memory management units (MMUs) for instructions and data.

–52-bit virtual address; 32-bit physical address.

–Address translation for virtual pages or variable-sized BAT blocks.

–Memory programmable as write-back or write-through, cacheable or noncacheable, and coherency enforced or coherency not enforced on a virtual-page or BAT block basis.

–Separate IBAT and DBAT arrays (eight each) for instructions and data, respectively.

–Separate virtual instruction and data translation lookaside buffers (TLBs).

•Both TLBs are 128-entry, 2-way set associative, and use an LRU replacement algorithm.

gx_01.fm.(1.2)

PowerPC 750GX Overview

March 27,2006

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