User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

one, two, or eight beats depending on the size of the program transaction and the cache mode for the address. For additional information about 32-bit data bus mode, see Section 8.6.1, 32-Bit Data Bus Mode, on page 316.”

8.1.5 Direct-Store Accesses

The 750GX does not support the extended transfer protocol for accesses to the direct-store storage space. The transfer protocol used for any given access is selected by the T bit in the MMU Segment Registers. If the T bit is set, the memory access is a direct-store access. An attempt to access instructions or data in a direct- store segment will result in the 750GX taking an instruction storage interrupt (ISI) or data-storage interrupt (DSI) exception.

Figure 8-2. Timing Diagram Legend

 

 

 

 

 

 

 

Note: A bar over signal name indicates active low.

 

 

ap0

 

 

750GX input (while 750GX is a bus master)

 

 

 

 

 

 

750GX output (while 750GX is a bus master)

 

 

BR

 

 

 

 

ADDR+

 

 

750GX output (grouped: here, address plus attributes)

 

 

 

 

750GX internal signal (inaccessible to the user, but used in diagrams to

qual BG

 

 

 

 

 

 

 

 

 

 

clarify operations)

 

 

 

 

 

 

 

Compelling dependency—event will occur on the next clock cycle

 

 

 

 

 

 

 

Prerequisite dependency—event will occur on an undetermined subsequent

 

 

 

 

 

 

 

clock cycle

 

 

 

 

 

 

 

750GX tristate output or input

 

 

 

 

 

 

 

750GX nonsampled input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal with sample point

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A sampled condition (dot on high or low state) with multiple dependencies

Timing for a signal had it been asserted (it is not actually asserted)

gx_08.fm.(1.2)

Bus Interface Operation

March 27, 2006

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