IBM 750GL, 750GX manual 223

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Figure 6-6. Instruction Timing—Cache Miss

0		1	2	3	4	5	6	7	8	9	10	11
	•••
	0 add									Fetch *
										In dispatch entry (IQ0/IQ1)
	1 fadd
										Execute
	2 add
										Complete (In CQ)
3 fadd
		4 b								In retirement entry (CQ0/CQ1)

5 fsub

Address

Data

6 fadd *

7 fadd *

8 add *

9 add *

10 add *

11 add *

12 fadd *

13 fadd *

Instruction

Queue

3	5
2	4
1	3	7		9
0	2	6	7	8

Completion

Queue

	3							9
	2	3	3				8
1	1	2	2			7	7
0	0	1	1	3	6	6	6

* Instructions 5 and 6 are not in the IQ in clock cycle 5. Here, the fetch stage shows cache latency.

gx_06.fm.(1.2)	Instruction Timing
March 27, 2006	Page 223 of 377