IBM 750GL, 750GX 4.5.13 Performance-MonitorInterrupt (0x00F00)

User’s Manual

IBM PowerPC 750GX and GL RISC Microprocessor

4.5.13 Performance-Monitor Interrupt (0x00F00)

The 750GX microprocessor provides a performance-monitor facility to monitor and count predefined events such as processor clocks, misses in either the instruction cache or the data cache, instructions dispatched to a particular execution unit, mispredicted branches, and other occurrences. The count of such events can be used to trigger the performance-monitor exception. The performance-monitor facility is not defined by the PowerPC Architecture.

The performance monitor can be used for the following situations:

•To increase system performance with efficient software, especially in a multiprocessing system. Memory hierarchy behavior must be monitored and studied to develop algorithms that schedule tasks (and per- haps partition them) and that structure and distribute data optimally.

•To help system developers bring up and debug their systems.

The performance monitor uses the following SPRs.

•The Performance-Monitor Counter Registers (PMC1–PMC4) are used to record the number of times a certain event has occurred. UPMC1–UPMC4 provide user-level read access to these registers.

•The Monitor Mode Control Registers (MMCR0–MMCR1) are used to enable various performance-moni- tor interrupt functions. UMMCR0–UMMCR1 provide user-level read access to these registers.

•The Sampled Instruction Address Register (SIA) contains the effective address of an instruction execut- ing at or around the time that the processor signals the performance-monitor interrupt condition. The USIA register provides user-level read access to the SIA.

Table 4-10lists register settings when a performance-monitor interrupt exception is taken.

Table 4-10. Performance-Monitor Interrupt Exception—Register Settings

Register					Setting Description
SRR0	Set to the effective address of the instruction that the processor would have attempted to execute next if no exception
	conditions were present.
	0	Loaded with equivalent MSR bits.
	1:4	Cleared.
SRR1	5:9	Loaded with equivalent MSR bits.
	10:15	Cleared.
	16:31	Loaded with equivalent MSR bits.
	POW	0	FP	0	BE	0	DR	0
MSR	ILE	—	ME	—	FE1	0	PM	0
	EE	0	FE0	0	IP	—	RI	0
	PR	0	SE	0	IR	0	LE	Set to value of ILE

As with other PowerPC exceptions, the performance-monitor interrupt follows the normal PowerPC exception model with a defined exception vector offset (0x00F00). The priority of the performance-monitor interrupt lies between the external interrupt and the decrementer interrupt (see Table 4-3on page 155). The contents of the SIA are described in Sampled Instruction Address Register (SIA) on page 75. The performance monitor is described in Chapter 11, Performance Monitor and System Related Features, on page 349.

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Page 172 of 377	March 27, 2006