User’s Manual

 

 

 

 

IBM PowerPC 750GX and 750GL RISC Microprocessor

 

 

 

 

 

Table 2-38. User-Level Cache Instructions (Page 2 of 2)

 

 

 

 

 

Name

Mnemonic

Syntax

 

Implementation Notes

 

 

 

 

 

 

 

 

 

 

 

The EA is computed, translated, and checked for protection violations.

 

 

 

 

• For cache hits with the tag marked exclusive unmodified (E), no further

 

 

 

 

action is taken.

 

 

 

 

• For cache hits with the tag marked M, the cache block is written back to

 

 

 

 

memory and marked exclusive unmodified (E).

Data Cache Block Store

dcbst

rA,rB

A dcbst is not broadcast unless HID0[ABE] = 1 regardless of WIMG settings.

 

 

 

The instruction acts like a load with respect to address translation and memory

 

 

 

protection. It executes regardless of whether the cache is disabled or locked.

 

 

 

The exception priorities (from highest to lowest) for dcbst are as follows:

 

 

 

1

BAT protection violation–DSI exception

 

 

 

2

TLB protection violation–DSI exception.

 

 

 

 

 

 

 

The EA is computed, translated, and checked for protection violations.

 

 

 

 

• For cache hits with the tag marked exclusive modified (M), the cache block

 

 

 

 

is written back to memory and the cache entry is invalidated.

 

 

 

 

• For cache hits with the tag marked exclusive unmodified (E), the entry is

 

 

 

 

invalidated.

Data Cache Block Flush

dcbf

rA,rB

 

• For cache misses, no further action is taken.

A dcbf is not broadcast unless HID0[ABE] = 1 regardless of WIMG settings.

 

 

 

 

 

 

The instruction acts like a load with respect to address translation and memory

 

 

 

protection. It executes regardless of whether the cache is disabled or locked.

 

 

 

The exception priorities (from highest to lowest) for dcbf are as follows:

 

 

 

1

BAT protection violation—DSI exception

 

 

 

2

TLB protection violation—DSI exception.

 

 

 

 

 

 

 

This instruction performs a virtual lookup into the instruction cache (index only).

Instruction Cache Block

icbi

rA,rB

The address is not translated, so it cannot cause an exception. All ways of a

Invalidate

selected set are invalidated regardless of whether the cache is disabled or

 

 

 

 

 

locked. The 750GX never broadcasts icbi onto the 60x bus.

 

 

 

 

 

1. A program that uses dcbt and dcbtst instructions improperly performs less efficiently. To improve performance, HID0[NOOPTI]

can be set, which causes dcbt and dcbtst to be no-oped at the cache. These instructions do not cause bus activity and cause only

a 1-clock execution latency. The default state of this bit is zero, which enables the use of these instructions.

 

 

 

 

 

 

2.3.5.4 Optional External Control Instructions

The PowerPC Architecture defines an optional external control feature that, if implemented, is supported by the two external control instructions, eciwx and ecowx. These instructions allow a user-level program to communicate with a special-purpose device. The instructions provided are summarized in Table 2-39.

Table 2-39. External Control Instructions

Name

Mnemonic

Syntax

Implementation Notes

 

 

 

 

 

 

 

 

 

 

External Control In

 

 

A transfer size of 4 bytes is implied. The

 

and TSIZ[0–2] signals are rede-

eciwx

rD,rA,rB

TBST

Word Indexed

 

 

fined to specify the Resource ID (RID), copied from bits EAR[28–31]. For these

 

 

 

operations, TBST carries the EAR[28] data. Misaligned operands for these

 

 

 

 

 

 

instructions cause an alignment exception. Addressing a location where

External Control Out

ecowx

rS,rA,rB

SR[T] = 1 causes a DSI exception. If MSR[DR] = 0, a programming error

Word Indexed

 

 

occurs and the physical address on the bus is undefined.

 

 

 

Note: These instructions are optional in the PowerPC Architecture.

 

 

 

 

 

 

The eciwx and ecowx instructions let a system designer map special devices in an alternative way. The MMU translation of the EA is not used to select the special device, as it is used in most instructions such as loads and stores. Rather, it is used as an address operand that is passed to the device over the address bus. Four other signals (the burst and size signals on the 60x bus) are used to select the device; these four signals

gx_02.fm.(1.2)

Programming Model

March 27, 2006

Page 117 of 377