IBM 750GL, 750GX State, Timing, 7.2.14.2 LSSD_MODE, 7.2.14 Test Interface Signals, 7.2.13 I/O Voltage Select Signals, 7.2.14.1 IEEE 1149.1a-1993Interface Description

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

7.2.13 I/O Voltage Select Signals

Table 7-7shows the settings for the I/O voltage signals.

Table 7-7. Bus Voltage Selection Settings

Voltage Selection	OVDD Select #1	OVDD Select #2
	BVSEL	L1TSTCLK
Reserved	0	0
1.8 V	0	1
2.5 V	1	1
3.3 V	1	0

7.2.14 Test Interface Signals

The processor provides two sets of pins for controlling JTAG and level-sensitive scan design (LSSD) testing.

7.2.14.1 IEEE 1149.1a-1993 Interface Description

The 750GX has five dedicated JTAG signals, which are described in Table 7-8. The test data input (TDI) and test data output (TDO) scan ports are used to scan instructions, as well as data into the various scan registers for JTAG operations. The scan operation is controlled by the test access port (TAP) controller, which in turn is controlled by the test mode select (TMS) input sequence. The scan data is latched in at the rising edge of the test clock (TCK). Test reset (TRST) is a JTAG optional signal, which is used to reset the TAP controller asynchronously. The TRST signal assures that the JTAG logic does not interfere with the normal operation of the chip, and must be asserted and deasserted coincident with the assertion of the HRESET signal.

Table 7-8. IEEE Interface Pin Descriptions

Signal Name		Input/Output	Weak Pullup Provided	IEEE 1149.1a-1993 Function		Timing Comments
	TDI	Input	Yes	Serial scan input signal	Asserted/Negated—Not used
					during normal operation. TMS,
	TDO	Output	No	Serial scan output signal
					TDI, and TRST have internal
					pullups provided; TCK does not.
	TMS	Input	Yes	TAP controller mode signal
					For normal operation, TMS and
	TCK	Input	No	Scan clock	TDI may be left unconnected,
					TCK must be set high or low,
					and	TRST	must be asserted
	TRST	Input	Yes	TAP controller reset	sometime during power-up for
					JTAG logic initialization.

7.2.14.2 LSSD_MODE
State	Asserted	LSSD test enable. The LSSD test enable signal is an input-only signal.
Timing	Assertion/	Must be set high by the system during normal operation.
	Negation

gx_07.fm.(1.2)	Signal Descriptions
March 27, 2006	Page 275 of 377