User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Index

A

AACK (address acknowledge) signal, 262 ABB (address bus busy) signal, 285 Address bus

address tenure, 284 address transfer

An, 254

APE, 294

address transfer attribute CI, 260

GBL, 261

TBST, 259, 294

TSIZn, 258, 294

TTn, 256, 294 WT, 260

address transfer start TS, 253, 292

address transfer termination AACK, 262

ARTRY, 263

terminating address transfer, 300 arbitration signals, 251, 285

bus parking, 291

Address translation, see Memory management unit Addressing modes, 89

Aligned data transfer, 296, 300 Alignment

data transfers, 296 exception, 170 misaligned accesses, 82 rules, 82

An (address bus) signals, 254

APE (address parity error) signal, 294 Arbitration, system bus, 290, 301 ARTRY (address retry) signal, 263

B

BG (bus grant) signal, 252, 285 Block address translation

block address translation flow, 189 definition, 33

registers description, 61 initialization, 196

selection of block address translation, 186 Boundedly undefined, definition, 87

BR (bus request) signal, 251, 285 Branch fall-through,226 Branch folding, 226

Branch instructions

address calculation, 106 condition register logical, 107 list of instructions, 107 system linkage, 108, 118 trap, 108

Branch prediction, 209, 229 Branch processing unit

branch instruction timing, 231 execution timing, 225 latency, branch instructions, 238 overview, 30

Branch resolution definition, 209

resource requirements, 237

BTIC (branch target instruction cache), 216 Burst data transfers

32-bit data bus, 296

64-bit data bus, 295

transfers with data delays, timing, 314 Bus arbitration, see Data bus

Bus configurations, 318

Bus interface unit (BIU), 122, 279 Bus transactions and L1 cache, 139 Byte ordering, 89

C

Cache arbitration, 217 block instructions

dcbi, data cache block invalidate, 119 dcbt, data cache block touch, 116

block, definition, 123

bus interface unit, 122, 279 cache operations

load/store operations, processor initiated, 130 operations, 136

overview, 281 cache unit overview, 123

cache-inhibited accesses (I bit), 125 characteristics, 121

coherency description, 125 overview, 142

reaction to bus operations, 143 control instructions, 131

bus operations, 141 data cache configuration, 123 dcbf/dcbst execution, 328 hit, 217

icbi, 328

instruction cache configuration, 124 instruction cache throttling, 347 integration, 122

L1 cache and bus transactions, 139

750gx_umIX.fm.(1.2)

Index

March 27, 2006

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