User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

5.1.3 Address-Translation Mechanisms

PowerPC processors support the following three types of address translation:

Page address

Translates the page frame address for a 4-KB page size.

Block address

Translates the block number for blocks that range in size from 128 KB to 256 MB.

Real-addressing

When address translation is disabled, the physical address is identical to the effec-

mode address

tive address.

Figure 5-4,Address-Translation Types shows the three address-translation mechanisms provided by the MMUs. The segment descriptors shown in the figure control the page-address-translation mechanism. When an access uses page-address translation, the appropriate segment descriptor is required. In 32-bit implemen- tations, the appropriate segment descriptor is selected from the 16 on-chip segment registers by the 4 highest-order effective address bits.

A control bit in the corresponding segment descriptor then determines if the access is to memory (memory- mapped) or to the direct-store interface space. Note that the direct-store interface was present in the architecture only for compatibility with existing I/O devices that use this interface. However, it is being removed from the architecture, and the 750GX does not support it. When an access is determined to be to the direct-store interface space, the 750GX takes a data-storage interrupt (DSI) exception if it is a data access (see Section 4.5.3, DSI Exception (0x00300), on page 169), and takes an instruction storage interrupt (ISI) exception if it is an instruction access (see Section 4.5.4, ISI Exception (0x00400), on page 169).

For memory accesses translated by a segment descriptor, the interim virtual address is generated using the information in the segment descriptor. Page-address translation corresponds to the conversion of this virtual address into the 32-bit physical address used by the memory subsystem. In most cases, the physical address for the page resides in an on-chip TLB and is available for quick access. However, if the page-address translation misses in the on-chip TLB, the MMU causes a search of the page tables in memory (using the virtual address information and a hashing function) to locate the required physical address.

Because blocks are larger than pages, there are fewer upper-order effective address bits to be translated into physical address bits (more low-order address bits (at least 17) are untranslated to form the offset into a block) for block-address translation. Also, instead of segment descriptors and a TLB, block-address translations use the on-chip BAT registers as a BAT array. If an effective address matches the corresponding field of a BAT register, the information in the BAT register is used to generate the physical address. In this case, the results of the page translation (occurring in parallel) are ignored.

Memory Management

gx_05.fm.(1.2)

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March 27, 2006