User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.1.2.2 Hardware-Implementation-Dependent Register 0 (HID0)

The Hardware-Implementation-Dependent Register 0 (HID0) controls the state of several functions within 750GX. HID0 can be accessed with mtspr and mfspr using SPR 1008.

EMCP

 

DBP

 

EBA

 

EBD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

2

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

4 5 6

PAR

 

DOZE

 

NAP

 

SLEEP

 

DPM

 

RISEG

 

Reserved

 

MUM

 

NHR

 

ICE

 

DCE

 

ILOCK

 

DLOCK

 

ICFI

 

DCFI

 

SPD

 

IFEM

 

SGE

 

DCFA

 

BTIC

 

Reserved

 

ABE

 

BHT

 

Reserved

 

NOOPTI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

8

 

9

 

10

 

11

 

12

 

13

 

14

 

15

 

16

 

17

 

18

 

19

 

20

 

21

 

22

 

23

 

24

 

25

 

26

 

27

 

28

 

29

 

30

 

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

Field Name

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enable

 

The primary purpose of this bit is to mask out further machine-check excep-

 

 

 

MCP.

 

 

 

tions caused by assertion of MCP, similar to how MSR[EE] can mask external interrupts.

 

 

 

 

 

 

Asserting

 

does not generate a machine-check exception or a

0

 

EMCP

0

Masks

MCP.

 

MCP

 

 

checkstop.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Asserting

MCP

causes a checkstop if MSR[ME] = 0 or a machine-check excep-

 

 

 

 

tion if ME = 1.

 

 

 

 

 

 

 

Disable 60x bus address-parity and data-parity generation.

 

 

 

0

Parity generation is enabled.

1

 

DBP

1

Disable parity generation. If the system does not use address or data parity and

 

 

the respective parity checking is disabled (HID0[EBA] or HID0[EBD] = 0), input

 

 

 

 

receivers for those signals are disabled, require no pull-up resistors, and thus

 

 

 

 

should be left unconnected. If all parity generation is disabled, all parity checking

 

 

 

 

should also be disabled and parity signals need not be connected.

 

 

 

 

 

 

 

Enable/disable 60x bus address-parity checking

 

 

 

0

Prevents address-parity checking.

2

 

EBA1

1

Allows an address-parity error to cause a checkstop if MSR[ME] = 0 or a

 

 

 

 

machine-check exception if MSR[ME] = 1.

 

 

 

EBA and EBD allow the processor to operate with memory subsystems that do not gener-

 

 

 

ate parity.

 

 

 

 

 

 

 

Enable 60x bus data-parity checking

 

 

 

0

Parity checking is disabled.

3

 

EBD1

1

Allows a data-parity error to cause a checkstop if MSR[ME] = 0 or a machine-

 

 

 

 

check exception if MSR[ME] = 1.

 

 

 

EBA and EBD allow the processor to operate with memory subsystems that do not gener-

 

 

 

ate parity.

 

 

 

 

4

 

—

Reserved. Must set to 0.

 

 

 

 

5

 

—

Not used. Defined as EICE on some earlier processors.

 

 

 

 

6

 

—

Reserved. Must set to 0.

 

 

 

 

 

 

 

 

 

 

 

Disable precharge of

 

 

 

 

 

 

 

 

 

 

 

 

ARTRY.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

Precharge of

ARTRY

enabled.

7

 

PAR

 

 

1

Alters bus protocol slightly by preventing the processor from driving

ARTRY

to

 

 

 

 

high (negated) state. If this is done, the system must restore the signals to the

 

 

 

 

high state.

 

 

 

 

 

 

 

Doze mode enable. Operates in conjunction with MSR[POW].

 

 

DOZE2

0

Doze mode disabled.

8

 

1

Doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit

 

 

 

 

is set. In doze mode, the phase-locked loop (PLL), time base, and snooping

 

 

 

 

remain active.

 

 

 

 

1. For additional information, see Section 11.9, Checkstops, on page 361.

2. For additional information about power-saving modes, see Table 10-2, HID0 Power Saving Mode Bit Settings, on page 337.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

gx_02.fm.(1.2)

 

 

 

 

 

 

 

 

 

 

 

 

 

Programming Model

March 27, 2006

 

 

 

 

 

 

 

 

 

 

 

 

 

Page 65 of 377