User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

6.5 Memory Performance Considerations

Because the 750GX can have a maximum instruction throughput of three instructions per clock cycle, lack of memory bandwidth can affect performance. For the 750GX to maximize performance, it must be able to read and write data efficiently. If a system has multiple bus devices, one of them might experience long memory latencies while another bus master (for example, a direct memory-access controller) is using the external bus.

6.5.1 Caching and Memory Coherency

To minimize the effect of bus contention, the PowerPC Architecture defines WIM bits that are used to configure memory regions as caching enforced or caching inhibited. Accesses to such memory locations never update the L1 cache. If a cache-inhibited access hits the L1 cache, the cache block is invalidated. If the cache block is marked modified, it is copied back to memory before being invalidated. Where caching is permitted, memory is configured as either write-back or write-through, which are described as follows:

Write-back

Configuring a memory region as write-back lets a processor modify data in the

 

cache without updating system memory. For such locations, memory updates

 

occur only on modified cache-block replacements, cache flushes, or when one

 

processor needs data that is modified in another’s cache. Therefore, configuring

 

memory as write-back can help when bus traffic could cause bottlenecks, espe-

 

cially for multiprocessor systems and for regions in which data, such as local vari-

 

ables, is used often and is coupled closely to a processor.

 

If multiple devices use data in a memory region marked write-through, snooping

 

must be enabled to allow the copy-back and cache invalidation operations neces-

 

sary to ensure cache coherency. The 750GX’s snooping hardware keeps other

 

devices from accessing invalid data. For example, when snooping is enabled, the

 

750GX monitors transactions of other bus devices. If another device needs data

 

that is modified on the 750GX’s cache, the access is delayed so the 750GX can

 

copy the modified data to memory.

Write-through

Store operations to memory marked write-through always update both system

 

memory and the L1 cache on cache hits. Because valid cache contents always

 

match system memory marked write-through, cache hits from other devices do not

 

cause modified data to be copied back as they do for locations marked write-back.

 

However, all write operations are passed to the bus, which can limit performance.

 

Load operations that miss the L1 cache must wait for the external store operation.

 

Write-through configuration is useful when cached data must agree with external

 

memory (for example, video memory), when shared (global) data might be needed

 

often, or when it is undesirable to allocate a cache block on a cache miss.

Chapter 3, Instruction-Cache and Data-Cache Operation, on page 121 describes the caches, memory config- uration, and snooping in detail.

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Instruction Timing

March 27, 2006

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