IBM 750GL, 750GX List of Figures

		User’s Manual
	IBM PowerPC 750GX and 750GL RISC Microprocessor
List of Figures
Figure 1-1.	750GX Microprocessor Block Diagram ..................................................................................	25
Figure 1-2.	L1 Cache Organization ..........................................................................................................	34
Figure 1-3.	System Interface ....................................................................................................................	37
Figure 1-4.	750GX Microprocessor Signal Groups ...................................................................................	39
Figure 1-5.	Pipeline Diagram ....................................................................................................................	53
Figure 2-1.	PowerPC 750GX Microprocessor Programming Model—Registers ......................................	58
Figure 3-1.	Cache Integration .................................................................................................................	122
Figure 3-2.	Data-Cache Organization .....................................................................................................	123
Figure 3-3.	Instruction-Cache Organization ............................................................................................	125
Figure 3-4.	MEI Cache-CoherencyProtocol—State Diagram (WIM = 001) ...........................................	128
Figure 3-5.	PLRU Replacement Algorithm .............................................................................................	137
Figure 3-6.	750GX Cache Addresses .....................................................................................................	140
Figure 4-1.	SRESET Asserted During HRESET ....................................................................................	164
Figure 5-1.	MMU Conceptual Block Diagram .........................................................................................	183
Figure 5-2.	PowerPC 750GX Microprocessor IMMU Block Diagram .....................................................	184
Figure 5-3.	750GX Microprocessor DMMU Block Diagram ....................................................................	185
Figure 5-4.	Address-Translation Types ..................................................................................................	187
Figure 5-5.	General Flow of Address Translation (Real-Addressing Mode and Block) ..........................	189
Figure 5-6.	General Flow of Page and Direct-Store Interface Address Translation ...............................	191
Figure 5-7.	Segment Register and DTLB Organization ..........................................................................	200
Figure 5-8.	Page-Address-TranslationFlow—TLB Hit ...........................................................................	203
Figure 5-9.	Primary Page Table Search .................................................................................................	205
Figure 5-10.	Secondary Page-Table-Search Flow ...................................................................................	206
Figure 6-1.	Pipelined Execution Unit ......................................................................................................	212
Figure 6-2.	Superscalar/Pipeline Diagram ..............................................................................................	212
Figure 6-3.	PowerPC 750GX Microprocessor Pipeline Stages ..............................................................	214
Figure 6-4.	Instruction Flow Diagram .....................................................................................................	218
Figure 6-5.	Instruction Timing—Cache Hit .............................................................................................	220
Figure 6-6.	Instruction Timing—Cache Miss ..........................................................................................	223
Figure 6-7.	Branch Taken .......................................................................................................................	227
Figure 6-8.	Removal of Fall-Through Branch Instruction ........................................................................	227
Figure 6-9.	Branch Completion ...............................................................................................................	228
Figure 6-10.	Branch Instruction Timing ....................................................................................................	231
Figure 7-1.	750GX Signal Groups ..........................................................................................................	250
Figure 8-1.	Bus Interface Address Buffers .............................................................................................	280
Figure 8-2.	Timing Diagram Legend .......................................................................................................	283
Figure 8-3.	Overlapping Tenures on the 750GX Bus for a Single-Beat Transfer ...................................	284
Figure 8-4.	Cache Diagram for Miss-under-Miss Feature ......................................................................	286
750gx_umLOF.fm.(1.2)		List of Figures
March 27, 2006		Page 13 of 377