IBM 750GL, 750GX 5.1.4 Memory-ProtectionFacilities

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Figure 5-4. Address-Translation Types

0

Address Translation Disabled

Effective Address

(MSR[IR] = 0, or MSR[DR] = 0)

	Segment Descriptor					Match with BAT
		Located				Registers
(T = 1)				(T = 0)
			Page Address			Block Address Translation
					(See Section 5.3 on page 196)
			Translation

0
	Virtual Address
Direct-Store Interface
Translation
		Look Up in		Real Addressing Mode
			Effective Address = Physical Address
		Page Table
				(See Section 5.2 on page 195)
DSI/ISI Exception

0	31	0	31	0		31
Physical Address			Physical Address		Physical Address

When the processor generates an access, and the corresponding address-translation-enable bit in the MSR is cleared, the resulting physical address is identical to the effective address, and all other translation mechanisms are ignored. Instruction address translation and data address translation are enabled by setting MSR[IR] and MSR[DR], respectively.

5.1.4 Memory-Protection Facilities

In addition to the translation of effective addresses to physical addresses, the MMUs provide access protection of supervisor areas from user access and can designate areas of memory as read-only, as well as no- execute or guarded. Table 5-2on page 188 shows the protection options supported by the MMUs for pages.

gx_05.fm.(1.2)	Memory Management
March 27, 2006	Page 187 of 377