IBM 750GL, 750GX 4.2 Exception Recognition and Priorities

		User’s Manual
		IBM PowerPC 750GX and GL RISC Microprocessor
Table 4-2. Exceptions and Conditions (Page 2 of 2)
Exception Type	Vector Offset	Causing Conditions
	(hex)
Program	00700	As defined by the PowerPC Architecture (for example, an instruction opcode error).
Floating-point unavail-	00800	As defined by the PowerPC Architecture. MSR[FP] = 0, and a floating-point instruction is
able		executed.
Decrementer	00900	As defined by the PowerPC Architecture, when the most-significant bit of the Decre-
		menter Register (DEC) changes from 0 to 1, and MSR[EE] = 1.
Reserved	00A00–00BFF	—
System call	00C00	Execution of the System Call (sc) instruction.
		MSR[SE] = 1, or a branch instruction is completing and MSR[BE] = 1. The 750GX differs
Trace	00D00	from the OEA by not taking this exception on an Instruction Synchronize (isync) instruc-
		tion.
Reserved	00E00	The 750GX does not generate an exception to this vector. Other PowerPC processors
		might use this vector for floating-point assist exceptions.
Reserved	00E10–00EFF	—
Performance monitor	00F00	The limit specified in PMCn is met and MMCR0[ENINT] = 1 (750GX-specific).
Instruction address	01300	IABR[0–29] matches EA[0–29] of the next instruction to complete, IABR[TE] matches
breakpoint		MSR[IR], and IABR[BE] = 1 (750GX-specific).
System management	01400	A system management exception is enabled if MSR[EE] = 1, and is signaled to the
exception		750GX by the assertion of an input signal pin, the system management interrupt (SMI).
Reserved	01500–016FF	—
Thermal-management	01700	Thermal management is enabled, junction temperature exceeds the threshold specified in
interrupt		THRM1 or THRM2, and MSR[EE] = 1 (750GX-specific).
Reserved	01800–02FFF	—

4.2 Exception Recognition and Priorities

Exceptions are roughly prioritized by exception class, as follows.

1.Nonmaskable, asynchronous exceptions have priority over all other exceptions. These are system reset and machine-check exceptions (although the machine-check exception condition can be disabled so the condition causes the processor to go directly into the checkstop state). These exceptions cannot be delayed and do not wait for completion of any precise-exception handling.

2.Synchronous, precise exceptions are caused by instructions and are taken in strict program order.

3.Imprecise exceptions (imprecise mode floating-point enabled exceptions) are caused by instructions, and they are delayed until higher-priority exceptions are taken. Note that the 750GX does not implement an exception of this type.

4.Maskable asynchronous exceptions (external, decrementer, thermal-management, system-management, performance-monitor, and interrupt exceptions) are delayed if higher-priority exceptions are taken.

The following list of exception categories describes how the 750GX handles exceptions up to the point of signaling the appropriate interrupt to occur. Note that a recoverable state is reached if the completed store queue is empty (drained, not cancelled), and the instruction that is next in program order has been signaled to complete and has completed. If MSR[RI] = 0, the 750GX is in a nonrecoverable state. Also, instruction completion is defined as updating all architectural registers associated with that instruction, and then removing that instruction from the completion buffer.

gx_04.fm.(1.2)	Exceptions
March 27, 2006	Page 153 of 377