User’s Manual

IBM PowerPC 750GX and GL RISC Microprocessor

0x000n_nnnn. If IP is set, exceptions are vectored to the physical address 0xFFFn_nnnn. For a machine- check exception that occurs when MSR[ME] = 0 (machine-check exceptions are disabled), the checkstop state is entered (the machine stops executing instructions).

4.3.6 Setting MSR[RI]

The RI bit in the MSR was designed to indicate to the exception handler whether the exception is recover- able. When an exception occurs, the RI bit is copied from the MSR to SRR1 and cleared in the MSR. All interrupts are disabled except machine checks. If a machine-check exception occurs while MSR[RI] is clear, a zero value is found in SRR1[RI] to indicate that the machine state is definitely not recoverable. When this bit is a one, the exception is recoverable as far as the current state of the machine and all programs are concerned including noncritical machine checks. An operating system might handle MSR[RI] as follows:

•In all exceptions, if SRR1[RI] is cleared, the machine state is not recoverable. If it is set, the exception is recoverable with respect to the processor and all programs.

•Use the general-purpose SPRs (SPRG0-SPRG3) registers to aid in saving the machine state. The follow- ing procedure is suggested:

–Point SPRG0 to a stack-saved area in memory

–Save three GPRs in SPRG1-SPRG3.

–Move SPRG0 into one of the GRPs that was saved. This GPR now points to the save area in mem- ory.

–Move the GPRs, SRR0, SRR1, SPRG1-3 and other registers to be used by the exception routine into the stack-saved area.

–Update SPGR0 to point to a new save area.

–Set MSR[RI] to indicate that machine state has been saved. Also set MSR[EE] if you want to re- enable external interrupts.

•When exception processing is complete, clear MSR[EE] and MSR[RI]. Adjust SPRG0 to point to the stack-saved area, restore the GPRs, SRR0 and SRR1, and any other register that you might have saved. Execute rfi. This returns the processor to the interrupted program.

4.3.7 Returning from an Exception Handler

The rfi instruction performs context synchronization by allowing previously-issued instructions to complete before returning to the interrupted process. In general, execution of the rfi instruction ensures the following:

•All previous instructions have completed to a point where they can no longer cause an exception. If a pre- vious instruction causes a direct-store interface error exception, the results must be determined before this instruction is executed.

•Previous instructions complete execution in the context (privilege, protection, and address translation) under which they were issued.

•The rfi instruction copies SRR1 bits back into the MSR.

•Instructions fetched after this instruction execute in the context established by this instruction.

•Program execution resumes at the instruction indicated by SRR0

For a complete description of context synchronization, see Chapter 6, “Exceptions,” of the PowerPC Microprocessor Family: The Programming Environments Manual.

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Exceptions

March 27, 2006

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