User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

7.2.5 Address Transfer Termination Signals

The address transfer termination signals are used to indicate either that the address phase of the transaction has completed successfully or must be repeated, and when it should be terminated. For detailed information about how these signals interact, see Chapter 8, Bus Interface Operation, on page 279.

7.2.5.1 Address Acknowledge (AACK)—Input

The address acknowledge (AACK) signal is an input-only signal on the 750GX.

State

Asserted

Indicates that the address tenure of a transaction should be terminated. On

 

 

the following cycle, the 750GX, as address-bus master, will release the

 

 

address and attribute signals to high impedance, and sample ARTRY to

 

 

determine a qualified ARTRY condition. Note that the address tenure will not

 

 

be terminated until the assertion of AACK, even if the associated data tenure

 

 

has completed. As snooper, the 750GX requires an assertion of AACK for

 

 

every assertion of TS that it detects.

 

 

 

 

 

 

 

 

 

 

Negated

During

ABB,

indicates that the address tenure must remain active, and that

 

 

the address and attribute signals remain driven.

Timing

 

 

 

 

 

 

Assertion/

May occur as early as the bus clock cycle after

TS

is asserted. Assertion can

 

Negation

be delayed to allow adequate address access time for slow devices. For

 

 

example, if an implementation supports slow snooping devices, an external

 

 

arbiter can postpone the assertion of AACK.

 

 

 

 

 

 

 

Note: If configured for 1x or 1.5x clock modes, the 750GX requires

AACK

to

 

 

be asserted no sooner than the second cycle following the assertion of TS

 

 

(one address wait state) in order to generate a snoop response (via

ARTRY)

.

Signal Descriptions

gx_07.fm.(1.2)

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March 27, 2006