IBM 750GL, 750GX tlbia, Notes:, 5.1.8 MMU Instructions and Register Summary

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Table 5-4. Other MMU Exception Conditions for the 750GX Processor (Page 2 of 2)

Condition	Description	Exception
eciwx or ecowx attempted when external	eciwx or ecowx attempted with EAR[E] = 0	DSI exception
control facility disabled		DSISR[11] = 1
Load Multiple Word (lmw), Store Multiple
Word (stmw), lswi, Load String Word
Immediate (lswx), Store String Word Imme-	lmw, stmw, lswi, lswx, stswi, or stswx	Alignment exception
diate (stswi), or Store String Word Indexed	instruction attempted while MSR[LE] = 1
x-form (stswx) instruction attempted in little-
endian mode
	Translation enabled and a floating-point
Operand misalignment	load/store, stmw, stwcx., lmw, lwarx,	Alignment exception (some of these cases
	eciwx, or ecowx instruction operand is not	are implementation-specific)
	word-aligned

5.1.8 MMU Instructions and Register Summary

The MMU instructions and registers allow the operating system to set up the block-address-translation areas and the page tables in memory.

Notes:

•Because the implementation of TLBs is optional, the instructions that refer to these structures are also optional. However, as these structures serve as caches of the page table, the architecture specifies a software protocol for maintaining coherency between these caches and the tables in memory whenever the tables in memory are modified. When the tables in memory are changed, the operating system purges these caches of the corresponding entries, allowing the translation caching mechanism to refetch from the tables when the corresponding entries are required.

•Also note that the 750GX implements all TLB-related instructions except TLB Invalidate All (tlbia), which is treated as an illegal instruction.

Because the MMU specification for PowerPC processors is so flexible, it is recommended that the software that uses these instructions and registers be encapsulated into subroutines to minimize the impact of migrating across the family of implementations.

Table 5-5summarizes the 750GX’s instructions that specifically control the MMU. For more detailed information about the instructions, see Chapter 2, Programming Model, on page 57 and Chapter 8, “Instruction Set,” in the PowerPC Microprocessor Family: The Programming Environments Manual.

Table 5-5. 750GX Microprocessor Instruction Summary—Control MMUs (Page 1 of 2)

Instruction Description

Move-to Segment Register

mtsr SR,rS← SR[SR#] rS

Move-to Segment Register Indirect

mtsrin rS,rB← SR[rB[0–3]] rS

Move-from Segment Register

mfsr rD,SR ←

rD SR[SR#]

Move-from Segment Register Indirect

mfsrin rD,rB ←

rD SR[rB[0–3]]

Memory Management	gx_05.fm.(1.2)
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