User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
5. Memory Management
This chapter describes the 750GX microprocessor’s implementation of the memory management unit (MMU) specifications provided by the operating environment architecture (OEA) for PowerPC processors. The primary function of the MMU in a PowerPC processor is the translation of logical (effective) addresses to physical addresses (referred to as real addresses in the architecture specification) for memory accesses and I/O accesses (I/O accesses are assumed to be memory-mapped). In addition, the MMU provides access protection on a segment, block, or page basis. This chapter describes the specific hardware used to implement the MMU model of the OEA in the 750GX. See Chapter 7, “Memory Management,” in the PowerPC Microprocessor Family: The Programming Environments Manual for a complete description of the conceptual model. Note that the 750GX does not implement the optional direct-store facility, and it is not likely to be supported in future devices.
Two general types of memory accesses generated by PowerPC processors require address translation— instruction accesses and data accesses generated by load-and-store instructions. Generally, the address- translation mechanism is defined in terms of the segment descriptors and page tables that PowerPC processors use to locate the effective-to-physical address mapping for memory accesses. The segment information translates the effective address to an interim virtual address, and the page table information translates the interim virtual address to a physical address.
The segment descriptors, used to generate the interim virtual addresses, are stored as on-chip segment registers on 32-bit implementations (such as the 750GX). In addition, two translation lookaside buffers (TLBs) are implemented on the 750GX to keep recently-used page-address translations on-chip. Although the PowerPC OEA describes one MMU (conceptually), the 750GX hardware maintains separate TLBs and table- search resources for instruction and data accesses that can be performed independently (and simulta- neously). Therefore, the 750GX is described as having two MMUs, one for instruction accesses (IMMU) and one for data accesses (DMMU).
The block-address translation (BAT) mechanism is a software-controlled array that stores the available block- address translations on-chip. BAT array entries are implemented as pairs of BAT registers that are accessible as supervisor special-purpose registers (SPRs). There are separate instruction and data BAT mechanisms,. In the 750GX, they reside in the instruction and data MMUs, respectively.
The MMUs, together with the exception processing mechanism, provide the necessary support for the operating system to implement a virtual memory environment and for enforcing protection of designated memory areas.
Exception processing is described in Chapter 4, Exceptions, on page 151. Specifically, Section 4.3, Exception Processing, on page 156 describes the Machine State Register (MSR), which controls some of the critical functionality of the MMUs.
5.1 MMU Overview
The 750GX implements the memory-management specification of the PowerPC OEA for 32-bit implementa- tions. Thus, it provides four gigabytes of effective address space accessible to supervisor and user programs, with a 4-KB page size and 256-MB segment size. In addition, the MMUs of 32-bit PowerPC processors use an interim virtual address (52 bits) and hashed page tables in the generation of 32-bit physical addresses.
PowerPC processors also have a BAT mechanism for mapping large blocks of memory. Block sizes range from 128 KB to 256 MB and are software-programmable.
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