User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

does not write back its results to the architected registers. Instead, it stalls in the completion queue. Of course, when the completion queue is full, no additional instructions can be dispatched, even if an execution unit is idle.

In the case of a misprediction, the 750GX can easily redirect the instruction stream because the programming model has not been updated. When a branch is mispredicted, all instructions that were dispatched after the predicted branch instruction are flushed from the completion queue, and any results are flushed from the Rename Registers.

The BTIC is a cache of two recently used instructions at the target (branch-to address) of branch instructions. If a taken-branch hits in the BTIC, two instructions are fed into the instruction queue on the next cycle. If a taken-branch misses in the BTIC, instruction fetching is done from the L1 instruction cache. Coherency of the BTIC table is maintained by table reset on an instruction-cache flash invalidate, icbi or rfi instruction execu- tion, or when an exception is taken.

In some situations, an instruction sequence creates dependencies that keep a branch instruction from being predicted because the address for the target of the branch is not available. This delays execution of the subsequent instruction stream. The instruction sequences and the resulting action of the branch instruction are as follows:

•An mtspr(LR) followed by a Branch Conditional to Link Register (bclr)—Fetching stops, and the branch waits for the mtspr to execute.

•An mtspr(CTR) followed by a Branch Conditional to Count Register (bcctr)—Fetching stops, and the branch waits for the mtspr to execute.

•An mtspr(CTR) followed by a bc (CTR decrement)—Fetching stops, and the branch waits for the mtspr to execute.

•A third bc (based on CR) is encountered while there are two unresolved bc (based on CR) instructions. The third bc (based on CR) is not executed, and fetching stops until one of the previous bc (based on CR) instructions is resolved. (Note that branch conditions can be a function of the CTR and the CR; if the CTR condition is sufficient to resolve the branch, then a CR-dependency is ignored.)

Static Branch Prediction

The PowerPC Architecture provides a field in branch instructions (the BO field) to allow software to speculate (hint) whether a branch is likely to be taken. Rather than delaying instruction processing until the condition is known, the 750GX uses the instruction encoding to predict whether the branch is likely to be taken and begins fetching and executing along that path. When the branch condition is known, the prediction is evalu- ated. If the prediction was correct, program flow continues along that path. Otherwise, the processor flushes any instructions and their results from the mispredicted path, and program flow resumes along the correct path.

Static branch prediction is used when HID0[BHT] is cleared. That is, the branch history table, which is used for dynamic branch prediction, is disabled.

For information about static branch prediction, see “Conditional Branch Control,” in Chapter 4, “Addressing Modes and Instruction Set Summary” in the PowerPC Microprocessor Family: The Programming Environments Manual.

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Instruction Timing

March 27, 2006

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