IBM 750GL, 750GX lmw, sync, eieio), Implementation Notes:

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

If store gathering is enabled and the stores do not fall under the above categories, then an Enforce In-Order Execution of I/O (eieio) or Synchronize (sync) instruction must be used to prevent two stores from being gathered.

Store gathering is also not done when the MMU is busy doing a hardware table walk.

Integer Load-and-Store with Byte-Reverse Instructions

Table 2-20describes integer load-and-store with byte-reverse instructions. When used in a PowerPC system operating with the default big-endian byte order, these instructions have the effect of loading and storing data in little-endian order. Likewise, when used in a PowerPC system operating with little-endian byte order, these instructions have the effect of loading and storing data in big-endian order. For more information about big- endian and little-endian byte ordering, see “Byte Ordering” in Chapter 3, “Operand Conventions” in the PowerPC Microprocessor Family: The Programming Environments Manual.

Table 2-20. Integer Load-and-Store with Byte-Reverse Instructions

Name	Mnemonic	Syntax
Load Half Word Byte-Reverse Indexed	lhbrx	rD,rA,rB
Load Word Byte-Reverse Indexed	lwbrx	rD,rA,rB
Store Half Word Byte-Reverse Indexed	sthbrx	rS,rA,rB
Store Word Byte-Reverse Indexed	stwbrx	rS,rA,rB

Integer Load-and-Store Multiple Instructions

The load/store multiple instructions are used to move blocks of data to and from the GPRs. The load multiple and store multiple instructions can have operands that require memory accesses that cross a 4-KB page boundary. As a result, these instructions might be interrupted by a DSI exception associated with the address translation of the second page.

Implementation Notes: The following describes the 750GX implementation of the load/store multiple instruc- tion.

•For load/store string operations, the hardware does not combine register values to reduce the number of discrete accesses. However, if store gathering is enabled and the accesses fall under the criteria for store gathering, the stores can be combined to enhance performance. At a minimum, additional cache access cycles are required.

•The 750GX supports misaligned, single-register load-and-store accesses in little-endian mode without causing an alignment exception. However, execution of misaligned load/store multiple/string operations causes an alignment exception.

The PowerPC Architecture defines the Load Multiple Word (lmw) instruction with rA in the range of registers to be loaded as an invalid form.

Table 2-21. Integer Load-and-Store Multiple Instructions

Name	Mnemonic	Syntax
Load Multiple Word	lmw	rD,d(rA)
Store Multiple Word	stmw	rS,d(rA)

Programming Model	gx_02.fm.(1.2)
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