User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

Each TLB contains 128 entries organized as a 2-way set-associative array with 64 sets as shown in Figure 5-7for the DTLB (the ITLB organization is the same). When an address is being translated, a set of two TLB entries is indexed in parallel with the access to a Segment Register. If the address in one of the two TLB entries is valid and matches the 40-bit virtual page number, that TLB entry contains the translation. If no match is found, a TLB miss occurs.

Figure 5-7. Segment Register and DTLB Organization

EA[0–31]

 

Segment Registers

 

 

 

 

 

0

7

8

31

 

 

 

 

 

 

 

 

 

0

 

T

 

 

 

 

 

EA[0–3]

 

 

 

 

VSID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

T

 

VSID

 

 

 

 

 

 

 

 

 

EA[4–13]

 

 

 

 

 

 

 

DTLB

V

0 V

Line 1

Compare

Line 0

Compare

EA[14–19] Select

63

 

 

 

 

 

Line1/Line 0 Hit

 

 

 

 

 

 

 

 

 

RPN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MUX

PA[0–19]

Unless the access is the result of an out-of-order access, a hardware table-search operation begins if there is a TLB miss. If the access is out of order, the table-search operation is postponed until the access is required, at which point the access is no longer out of order. When the matching PTE is found in memory, it is loaded into the TLB entry selected by the LRU replacement algorithm, and the translation process begins again, this time with a TLB hit.

Memory Management

gx_05.fm.(1.2)

Page 200 of 377

March 27, 2006