User’s Manual

 

 

IBM PowerPC 750GX and 750GL RISC Microprocessor

 

Figure 8-5.

First Level Address Pipelining ..............................................................................................

287

Figure 8-6.

Address-Bus Arbitration ........................................................................................................

290

Figure 8-7.

Address-Bus Arbitration Showing Bus Parking ....................................................................

291

Figure 8-8.

Address-Bus Transfer ...........................................................................................................

293

Figure 8-9.

Snooped Address Cycle with ARTRY ..................................................................................

301

Figure 8-10.

Data-Bus Arbitration .............................................................................................................

302

Figure 8-11.

Normal Single-Beat Read Termination .................................................................................

304

Figure 8-12.

Normal Single-Beat Write Termination .................................................................................

305

Figure 8-13.

Normal Burst Transaction .....................................................................................................

305

Figure 8-14.

Termination with DRTRY ......................................................................................................

306

Figure 8-15.

Read Burst with TA Wait States and DRTRY .......................................................................

307

Figure 8-16.

MEI Cache-CoherencyProtocol—State Diagram (WIM = 001) ...........................................

309

Figure 8-17.

Fastest Single-Beat Reads ...................................................................................................

310

Figure 8-18.

Fastest Single-Beat Writes ...................................................................................................

311

Figure 8-19.

Single-Beat Reads Showing Data-Delay Controls ...............................................................

312

Figure 8-20.

Single-Beat Writes Showing Data-Delay Controls ................................................................

313

Figure 8-21.

Burst Transfers with Data-Delay Controls ............................................................................

314

Figure 8-22.

Use of Transfer Error Acknowledge (TEA) ...........................................................................

315

Figure 8-23.

32-BitData-Bus Transfer (8-Beat Burst) ..............................................................................

317

Figure 8-24.

32-BitData-Bus Transfer (2-Beat Burst with DRTRY) ..........................................................

317

Figure 8-25.

IEEE 1149.1a-1993 Compliant Boundary-Scan Interface ....................................................

320

Figure 8-26.

Data-BusWrite-Only Transaction .........................................................................................

320

Figure 9-1.

L2 Cache ..............................................................................................................................

327

Figure 10-1.

750GX Power States ............................................................................................................

336

Figure 10-2.

Dual PLL Block Diagram ......................................................................................................

342

Figure 10-3.

Dual PLL Switching Example, 3X to 4X ................................................................................

343

Figure 10-4.

Thermal Assist Unit Block Diagram ......................................................................................

344

Figure 10-5.

Instruction Cache Throttling Control SPR Diagram ..............................................................

347

Figure 11-1.

750GX IEEE 1149.1a-1993/COP Organization ....................................................................

358

Figure 11-2.

Reset Sequence ...................................................................................................................

360

List of Figures

750gx_umLOF.fm.(1.2)

Page 14 of 377

March 27, 2006